| /external/arm-trusted-firmware/drivers/arm/gic/v2/ |
| D | gicv2_main.c | 39 assert(driver_data->gicc_base != 0U); in gicv2_cpuif_enable()
49 gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK); in gicv2_cpuif_enable()
50 gicc_write_ctlr(driver_data->gicc_base, val); in gicv2_cpuif_enable()
62 assert(driver_data->gicc_base != 0U); in gicv2_cpuif_disable()
65 val = gicc_read_ctlr(driver_data->gicc_base); in gicv2_cpuif_disable()
69 gicc_write_ctlr(driver_data->gicc_base, val); in gicv2_cpuif_disable()
133 assert(plat_driver_data->gicc_base != 0U); in gicv2_driver_init()
182 assert(driver_data->gicc_base != 0U); in gicv2_is_fiq_enabled()
184 gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base); in gicv2_is_fiq_enabled()
199 assert(driver_data->gicc_base != 0U); in gicv2_get_pending_interrupt_type()
[all …]
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| /external/arm-trusted-firmware/plat/layerscape/common/tsp/ |
| D | ls_tsp_setup.c | 23 .gicc_base = GICC_BASE,
48 uint32_t gicc_base, gicd_base; in tsp_platform_setup() local
51 get_gic_offset(&gicc_base, &gicd_base); in tsp_platform_setup()
53 ls_gic_data.gicc_base = (uintptr_t)gicc_base; in tsp_platform_setup()
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| /external/arm-trusted-firmware/plat/layerscape/board/ls1043/ |
| D | ls_gic.c | 23 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base) in get_gic_offset() argument
39 *gicc_base = GICC_BASE; in get_gic_offset()
42 *gicc_base = GICC_BASE_64K; in get_gic_offset()
46 *gicc_base = GICC_BASE; in get_gic_offset()
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| /external/arm-trusted-firmware/plat/layerscape/common/ |
| D | ls_bl31_setup.c | 33 .gicc_base = GICC_BASE,
151 uint32_t gicc_base, gicd_base; in ls_bl31_platform_setup() local
155 get_gic_offset(&gicc_base, &gicd_base); in ls_bl31_platform_setup()
157 ls_gic_data.gicc_base = (uintptr_t)gicc_base; in ls_bl31_platform_setup()
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| /external/arm-trusted-firmware/plat/layerscape/common/include/ |
| D | soc.h | 16 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
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| /external/arm-trusted-firmware/plat/qemu/common/ |
| D | qemu_gicv2.c | 18 .gicc_base = GICC_BASE,
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| /external/arm-trusted-firmware/plat/mediatek/mt6795/ |
| D | plat_mt_gic.c | 20 .gicc_base = BASE_GICC_BASE,
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| /external/arm-trusted-firmware/plat/rockchip/common/ |
| D | rockchip_gicv2.c | 38 .gicc_base = PLAT_RK_GICC_BASE,
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| /external/arm-trusted-firmware/plat/hisilicon/poplar/ |
| D | poplar_gicv2.c | 25 .gicc_base = POPLAR_GICC_BASE,
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| /external/arm-trusted-firmware/plat/nvidia/tegra/common/ |
| D | tegra_gicv2.c | 36 tegra_gic_data.gicc_base = TEGRA_GICC_BASE; in tegra_gic_setup()
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| /external/arm-trusted-firmware/plat/arm/common/ |
| D | arm_gicv2.c | 36 .gicc_base = PLAT_ARM_GICC_BASE,
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| /external/arm-trusted-firmware/plat/marvell/armada/common/ |
| D | marvell_gicv2.c | 59 .gicc_base = PLAT_MARVELL_GICC_BASE,
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| /external/arm-trusted-firmware/plat/amlogic/gxbb/ |
| D | gxbb_bl31_setup.c | 129 .gicc_base = AML_GICC_BASE,
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| /external/arm-trusted-firmware/plat/hisilicon/hikey/ |
| D | hikey_bl31_setup.c | 50 .gicc_base = PLAT_ARM_GICC_BASE,
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| /external/arm-trusted-firmware/plat/qemu/common/sp_min/ |
| D | sp_min_setup.c | 63 .gicc_base = GICC_BASE,
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| /external/arm-trusted-firmware/plat/amlogic/g12a/ |
| D | g12a_bl31_setup.c | 129 .gicc_base = AML_GICC_BASE,
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| /external/arm-trusted-firmware/plat/allwinner/common/ |
| D | sunxi_bl31_setup.c | 35 .gicc_base = SUNXI_GICC_BASE,
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| /external/arm-trusted-firmware/plat/amlogic/gxl/ |
| D | gxl_bl31_setup.c | 145 .gicc_base = AML_GICC_BASE,
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| /external/arm-trusted-firmware/plat/amlogic/axg/ |
| D | axg_bl31_setup.c | 155 .gicc_base = AML_GICC_BASE,
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| /external/arm-trusted-firmware/include/drivers/arm/ |
| D | gicv2.h | 152 uintptr_t gicc_base; member
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| /external/arm-trusted-firmware/plat/rpi/rpi4/ |
| D | rpi4_bl31_setup.c | 39 .gicc_base = RPI4_GIC_GICC_BASE,
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| /external/arm-trusted-firmware/plat/intel/soc/agilex/ |
| D | bl31_plat_setup.c | 92 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
|
| /external/arm-trusted-firmware/plat/intel/soc/stratix10/ |
| D | bl31_plat_setup.c | 100 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
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| /external/arm-trusted-firmware/plat/hisilicon/hikey960/ |
| D | hikey960_bl31_setup.c | 47 .gicc_base = GICC_REG_BASE,
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| D | hikey960_bl1_setup.c | 59 .gicc_base = GICC_REG_BASE,
|