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Searched refs:hasSuperClassEq (Results 1 – 25 of 33) sorted by relevance

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/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVMCInstLower.cpp171 if (RC->hasSuperClassEq(&RISCV::VRM2RegClass) || in lowerRISCVVMachineInstrToMCInst()
172 RC->hasSuperClassEq(&RISCV::VRM4RegClass) || in lowerRISCVVMachineInstrToMCInst()
173 RC->hasSuperClassEq(&RISCV::VRM8RegClass)) { in lowerRISCVVMachineInstrToMCInst()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
517 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
518 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
534 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
540 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
DThumb1InstrInfo.cpp111 (RC->hasSuperClassEq(&ARM::tGPRRegClass) || in loadRegFromStackSlot()
115 if (RC->hasSuperClassEq(&ARM::tGPRRegClass) || in loadRegFromStackSlot()
/external/llvm-project/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
517 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
518 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
534 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
540 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
DThumb1InstrInfo.cpp111 (RC->hasSuperClassEq(&ARM::tGPRRegClass) || in loadRegFromStackSlot()
115 if (RC->hasSuperClassEq(&ARM::tGPRRegClass) || in loadRegFromStackSlot()
/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp142 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
280 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
531 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || in optimizeAllLanesPattern()
532 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { in optimizeAllLanesPattern()
548 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { in optimizeAllLanesPattern()
554 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) && in optimizeAllLanesPattern()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
124 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
126 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
/external/llvm-project/llvm/lib/Target/X86/
DX86SpeculativeLoadHardening.cpp1667 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()
1668 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()
1670 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
1704 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
1705 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
1706 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
1708 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
1709 bool Is256Bit = OpRC->hasSuperClassEq(&X86::VR256XRegClass); in hardenLoadAddr()
1737 assert(OpRC->hasSuperClassEq(&X86::GR64RegClass) && in hardenLoadAddr()
1893 return RC->hasSuperClassEq(GPRRegClasses[RegIdx]); in canHardenRegister()
DX86RegisterInfo.cpp221 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 && in shouldRewriteCopySrc()
222 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit) in shouldRewriteCopySrc()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86SpeculativeLoadHardening.cpp2040 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || in hardenLoadAddr()
2041 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { in hardenLoadAddr()
2043 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); in hardenLoadAddr()
2077 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || in hardenLoadAddr()
2078 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || in hardenLoadAddr()
2079 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { in hardenLoadAddr()
2081 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); in hardenLoadAddr()
2082 bool Is256Bit = OpRC->hasSuperClassEq(&X86::VR256XRegClass); in hardenLoadAddr()
2110 assert(OpRC->hasSuperClassEq(&X86::GR64RegClass) && in hardenLoadAddr()
2263 return RC->hasSuperClassEq(GPRRegClasses[RegIdx]); in canHardenRegister()
DX86RegisterInfo.cpp226 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 && in shouldRewriteCopySrc()
227 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit) in shouldRewriteCopySrc()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp483 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad()
505 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad()
626 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitStore()
1187 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in SelectBinaryIntOp()
2012 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCMaterialize32BitInt()
DPPCInstrInfo.cpp158 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
159 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp476 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad()
496 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad()
630 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitStore()
1284 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in SelectBinaryIntOp()
2117 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCMaterialize32BitInt()
DPPCInstrInfo.cpp192 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
193 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
3847 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? in transformToImmFormFedByLI()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp477 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad()
497 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad()
631 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitStore()
1287 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in SelectBinaryIntOp()
2131 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCMaterialize32BitInt()
DPPCInstrInfo.cpp172 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
173 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
4630 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? in transformToImmFormFedByLI()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h161 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() function
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp350 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && in shouldCoalesce()
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.cpp349 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) && in shouldCoalesce()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h135 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() function
/external/llvm-project/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h135 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq() function
/external/llvm/lib/CodeGen/
DMachineVerifier.cpp1043 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()

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