Searched refs:htile_offset (Results 1 – 15 of 15) sorted by relevance
| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_texture.c | 426 rtex->htile_offset = new_tex->htile_offset; in r600_reallocate_texture_inplace()
433 assert(!rtex->htile_offset); in r600_reallocate_texture_inplace()
821 rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment); in r600_texture_allocate_htile()
822 rtex->size = rtex->htile_offset + rtex->surface.htile_size; in r600_texture_allocate_htile()
861 if (rtex->htile_offset) in r600_print_texture_info()
864 rtex->htile_offset, rtex->surface.htile_size, in r600_print_texture_info()
998 if (rtex->htile_offset) { in r600_texture_create_object()
1002 rtex->htile_offset, in r600_texture_create_object()
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| D | r600_pipe_common.h | 225 uint64_t htile_offset; member
900 return tex->htile_offset && level == 0; in r600_htile_enabled()
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| D | r600_state.c | 1072 surf->db_htile_data_base = rtex->htile_offset >> 8; in r600_init_depth_surface()
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| D | evergreen_state.c | 1430 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset; in evergreen_init_depth_surface()
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| /external/mesa3d/src/amd/common/ |
| D | ac_surface.h | 250 uint64_t htile_offset; member
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| D | ac_surface.c | 2113 surf->htile_offset = 0; in ac_compute_surface()
2116 surf->htile_offset = align64(surf->total_size, surf->htile_alignment); in ac_compute_surface()
2117 surf->total_size = surf->htile_offset + surf->htile_size; in ac_compute_surface()
2484 if (surf->htile_offset) in ac_surface_override_offset_stride()
2485 surf->htile_offset += offset; in ac_surface_override_offset_stride()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_texture.c | 519 tex->surface.htile_offset = new_tex->surface.htile_offset; in si_reallocate_texture_inplace()
541 assert(!tex->surface.htile_offset); in si_reallocate_texture_inplace()
867 if (tex->surface.htile_offset) { in si_print_texture_info()
870 tex->surface.htile_offset, tex->surface.htile_size, in si_print_texture_info()
914 if (tex->surface.htile_offset) in si_print_texture_info()
918 tex->surface.htile_offset, tex->surface.htile_size, tex->surface.htile_alignment, in si_print_texture_info()
1098 if (tex->surface.htile_offset) { in si_texture_create_object()
1104 si_screen_clear_buffer(sscreen, &tex->buffer.b.b, tex->surface.htile_offset, in si_texture_create_object()
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| D | si_pipe.h | 1770 return tex->surface.htile_offset && level == 0; in si_htile_enabled()
1776 assert(!tex->tc_compatible_htile || tex->surface.htile_offset); in vi_tc_compat_htile_enabled()
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| D | si_clear.c | 609 si_clear_buffer(sctx, &zstex->buffer.b.b, zstex->surface.htile_offset, in si_clear()
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| D | si_state.c | 2442 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.htile_offset) >> 8; in si_init_depth_surface()
2513 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.htile_offset) >> 8; in si_init_depth_surface()
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| D | si_descriptors.c | 350 meta_va = tex->buffer.gpu_address + tex->surface.htile_offset; in si_set_mutable_tex_desc_fields()
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| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_surface.c | 442 surf_ws->htile_offset = align64(surf_ws->total_size, surf_ws->htile_alignment); in radeon_winsys_surface_init()
443 surf_ws->total_size = surf_ws->htile_offset + surf_ws->htile_size; in radeon_winsys_surface_init()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 668 meta_va = gpu_address + plane->surface.htile_offset; in si_set_mutable_tex_desc_fields()
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| D | radv_meta_clear.c | 1570 uint64_t offset = image->offset + image->planes[0].surface.htile_offset + in radv_clear_htile()
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| D | radv_device.c | 7078 surf->htile_offset; in radv_initialise_ds_surface()
7146 surf->htile_offset; in radv_initialise_ds_surface()
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