| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | fast-isel-sp-adjust.ll | 22 call void @bar(i64 undef, i64 undef, i64 undef, i64 undef,
23 i64 undef, i64 undef, i64 undef, i64 undef, ; All regs gone.
24 i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 32
25 i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 64
26 i64 undef, i64 undef, i64 undef, i64 undef,
27 i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 128
28 i64 undef, i64 undef, i64 undef, i64 undef,
29 i64 undef, i64 undef, i64 undef, i64 undef,
30 i64 undef, i64 undef, i64 undef, i64 undef,
31 i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 256
[all …]
|
| /external/llvm-project/llvm/test/Transforms/InstCombine/X86/ |
| D | clmulqdq.ll | 4 declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8)
5 declare <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64>, <4 x i64>, i8)
6 declare <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64>, <8 x i64>, i8)
8 define <2 x i64> @test_demanded_elts_pclmulqdq_0(<2 x i64> %a0, <2 x i64> %a1) {
10 ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> [[A0:%.*]], <2 x i64> …
11 ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
13 %1 = insertelement <2 x i64> %a0, i64 1, i64 1
14 %2 = insertelement <2 x i64> %a1, i64 1, i64 1
15 %3 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %2, i8 0)
16 ret <2 x i64> %3
[all …]
|
| /external/llvm-project/llvm/test/Instrumentation/MemorySanitizer/X86/ |
| D | vararg-too-large.ll | 8 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
11 define dso_local i64 @many_args() {
13 %ret = call i64 (i64, ...) @sum(i64 120,
14 i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
15 i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
16 i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
17 i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
18 i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
19 i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
20 i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1,
[all …]
|
| /external/llvm-project/llvm/test/Assembler/ |
| D | flags.ll | 4 @addr = external global i64
6 define i64 @add_unsigned(i64 %x, i64 %y) {
7 ; CHECK: %z = add nuw i64 %x, %y
8 %z = add nuw i64 %x, %y
9 ret i64 %z
12 define i64 @sub_unsigned(i64 %x, i64 %y) {
13 ; CHECK: %z = sub nuw i64 %x, %y
14 %z = sub nuw i64 %x, %y
15 ret i64 %z
18 define i64 @mul_unsigned(i64 %x, i64 %y) {
[all …]
|
| /external/llvm/test/Assembler/ |
| D | flags.ll | 4 @addr = external global i64
6 define i64 @add_unsigned(i64 %x, i64 %y) {
7 ; CHECK: %z = add nuw i64 %x, %y
8 %z = add nuw i64 %x, %y
9 ret i64 %z
12 define i64 @sub_unsigned(i64 %x, i64 %y) {
13 ; CHECK: %z = sub nuw i64 %x, %y
14 %z = sub nuw i64 %x, %y
15 ret i64 %z
18 define i64 @mul_unsigned(i64 %x, i64 %y) {
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | keylocker-intrinsics-fast-isel.ll | 6 define void @test_loadiwkey(i32 %ctl, <2 x i64> %intkey, <2 x i64> %enkey_lo, <2 x i64> %enkey_hi) {
13 …tail call void @llvm.x86.loadiwkey(<2 x i64> %intkey, <2 x i64> %enkey_lo, <2 x i64> %enkey_hi, i3…
17 define i32 @test_encodekey128_u32(i32 %htype, <2 x i64> %key, i8* nocapture %h) {
29 …= tail call { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.en…
30 %1 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 1
31 %2 = bitcast i8* %h to <2 x i64>*
32 store <2 x i64> %1, <2 x i64>* %2, align 1
33 %3 = extractvalue { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %0, 2
34 %4 = getelementptr i8, i8* %h, i64 16
35 %5 = bitcast i8* %4 to <2 x i64>*
[all …]
|
| D | 2009-04-16-SpillerUnfold.ll | 8 %struct.SHA512_CTX = type { [8 x i64], i64, i64, %struct.anon, i32, i32 }
9 %struct.anon = type { [16 x i64] }
10 @K512 = external constant [80 x i64], align 32 ; <[80 x i64]*> [#uses=2]
12 …12_block_data_order(%struct.SHA512_CTX* nocapture %ctx, i8* nocapture %in, i64 %num) nounwind ssp {
17 %e.0489 = phi i64 [ 0, %entry ], [ %e.0, %bb349 ] ; <i64> [#uses=3]
18 %b.0472 = phi i64 [ 0, %entry ], [ %87, %bb349 ] ; <i64> [#uses=2]
19 …%asmtmp356 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 41, i64 %e.…
20 %0 = xor i64 0, %asmtmp356 ; <i64> [#uses=1]
21 %1 = add i64 0, %0 ; <i64> [#uses=1]
22 %2 = add i64 %1, 0 ; <i64> [#uses=1]
[all …]
|
| D | 2009-06-02-RewriterBug.ll | 4 define void @sha256_block1(i32* nocapture %arr, i8* nocapture %in, i64 %num) nounwind {
12 %indvar2787 = phi i64 [ 0, %bb.nph ], [ %indvar.next2788, %for.end ] ; <i64> [#uses=2]
13 %tmp2791 = mul i64 %indvar2787, 44 ; <i64> [#uses=0]
14 %ctg22996 = getelementptr i8, i8* %in, i64 0 ; <i8*> [#uses=1]
15 %conv = zext i32 undef to i64 ; <i64> [#uses=1]
16 %conv11 = zext i32 undef to i64 ; <i64> [#uses=1]
18 %conv19 = zext i32 %tmp18 to i64 ; <i64> [#uses=1]
20 %conv31 = zext i32 %tmp30 to i64 ; <i64> [#uses=4]
22 %conv442709 = zext i8 %ptrincdec3065 to i64 ; <i64> [#uses=1]
23 %shl45 = shl i64 %conv442709, 16 ; <i64> [#uses=1]
[all …]
|
| D | keylocker-intrinsics.ll | 7 declare void @llvm.x86.loadiwkey(<2 x i64>, <2 x i64>, <2 x i64>, i32)
8 declare { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.encodek…
9 …are { i32, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86…
10 declare { i8, <2 x i64> } @llvm.x86.aesenc128kl(<2 x i64>, i8*)
11 declare { i8, <2 x i64> } @llvm.x86.aesdec128kl(<2 x i64>, i8*)
12 declare { i8, <2 x i64> } @llvm.x86.aesenc256kl(<2 x i64>, i8*)
13 declare { i8, <2 x i64> } @llvm.x86.aesdec256kl(<2 x i64>, i8*)
14 …i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.aese…
15 …i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.aesd…
16 …i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.x86.aese…
[all …]
|
| /external/llvm/test/CodeGen/X86/ |
| D | 2009-04-16-SpillerUnfold.ll | 8 %struct.SHA512_CTX = type { [8 x i64], i64, i64, %struct.anon, i32, i32 }
9 %struct.anon = type { [16 x i64] }
10 @K512 = external constant [80 x i64], align 32 ; <[80 x i64]*> [#uses=2]
12 …12_block_data_order(%struct.SHA512_CTX* nocapture %ctx, i8* nocapture %in, i64 %num) nounwind ssp {
17 %e.0489 = phi i64 [ 0, %entry ], [ %e.0, %bb349 ] ; <i64> [#uses=3]
18 %b.0472 = phi i64 [ 0, %entry ], [ %87, %bb349 ] ; <i64> [#uses=2]
19 …%asmtmp356 = call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 41, i64 %e.…
20 %0 = xor i64 0, %asmtmp356 ; <i64> [#uses=1]
21 %1 = add i64 0, %0 ; <i64> [#uses=1]
22 %2 = add i64 %1, 0 ; <i64> [#uses=1]
[all …]
|
| D | 2009-03-23-MultiUseSched.ll | 10 @X = external global i64 ; <i64*> [#uses=25]
12 define fastcc i64 @foo() nounwind {
13 %tmp = load volatile i64, i64* @X ; <i64> [#uses=7]
14 %tmp1 = load volatile i64, i64* @X ; <i64> [#uses=5]
15 %tmp2 = load volatile i64, i64* @X ; <i64> [#uses=3]
16 %tmp3 = load volatile i64, i64* @X ; <i64> [#uses=1]
17 %tmp4 = load volatile i64, i64* @X ; <i64> [#uses=5]
18 %tmp5 = load volatile i64, i64* @X ; <i64> [#uses=3]
19 %tmp6 = load volatile i64, i64* @X ; <i64> [#uses=2]
20 %tmp7 = load volatile i64, i64* @X ; <i64> [#uses=1]
[all …]
|
| D | 2009-06-02-RewriterBug.ll | 4 define void @sha256_block1(i32* nocapture %arr, i8* nocapture %in, i64 %num) nounwind {
12 %indvar2787 = phi i64 [ 0, %bb.nph ], [ %indvar.next2788, %for.end ] ; <i64> [#uses=2]
13 %tmp2791 = mul i64 %indvar2787, 44 ; <i64> [#uses=0]
14 %ctg22996 = getelementptr i8, i8* %in, i64 0 ; <i8*> [#uses=1]
15 %conv = zext i32 undef to i64 ; <i64> [#uses=1]
16 %conv11 = zext i32 undef to i64 ; <i64> [#uses=1]
18 %conv19 = zext i32 %tmp18 to i64 ; <i64> [#uses=1]
20 %conv31 = zext i32 %tmp30 to i64 ; <i64> [#uses=4]
22 %conv442709 = zext i8 %ptrincdec3065 to i64 ; <i64> [#uses=1]
23 %shl45 = shl i64 %conv442709, 16 ; <i64> [#uses=1]
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vldm-sched-a9.ll | 3 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v…
11 define void @test(i64* %src) #0 {
13 %arrayidx39 = getelementptr inbounds i64, i64* %src, i32 13
14 …i64> undef, <16 x i64> <i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64…
15 store <16 x i64> %vecinit285, <16 x i64>* undef, align 128
16 %0 = load i64, i64* undef, align 8
17 %vecinit379 = insertelement <16 x i64> undef, i64 %0, i32 9
18 %1 = load i64, i64* undef, align 8
19 %vecinit419 = insertelement <16 x i64> undef, i64 %1, i32 15
20 store <16 x i64> %vecinit419, <16 x i64>* undef, align 128
[all …]
|
| /external/llvm-project/llvm/test/Instrumentation/MemorySanitizer/Mips/ |
| D | vararg-mips64el.ll | 4 target datalayout = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"
10 call void @llvm.lifetime.start.p0i8(i64 32, i8* %1)
13 call void @llvm.lifetime.end.p0i8(i64 32, i8* %1)
21 ; CHECK: [[B:%.*]] = add i64 0, [[A]]
24 …: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_a…
26 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
29 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
32 %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.000000e+00)
39 ; CHECK: store i32 0, i32* bitcast ([100 x i64]* @__msan_va_arg_tls to i32*), align 8
40 ; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64)…
[all …]
|
| D | vararg-mips64.ll | 4 target datalayout = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"
10 call void @llvm.lifetime.start.p0i8(i64 32, i8* %1)
13 call void @llvm.lifetime.end.p0i8(i64 32, i8* %1)
21 ; CHECK: [[B:%.*]] = add i64 0, [[A]]
24 …: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_a…
26 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
29 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
32 %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.000000e+00)
40 ; CHECK: store i32 0, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64)…
41 ; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64)…
[all …]
|
| /external/llvm-project/llvm/test/Instrumentation/MemorySanitizer/PowerPC/ |
| D | vararg-ppc64.ll | 4 target datalayout = "E-m:e-i64:64-n32:64"
10 call void @llvm.lifetime.start.p0i8(i64 32, i8* %1)
13 call void @llvm.lifetime.end.p0i8(i64 32, i8* %1)
21 ; CHECK: [[B:%.*]] = add i64 0, [[A]]
24 …: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_a…
26 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
29 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
32 %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.000000e+00)
40 ; CHECK: store i32 0, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64)…
41 ; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64)…
[all …]
|
| D | vararg-ppc64le.ll | 4 target datalayout = "e-m:e-i64:64-n32:64"
10 call void @llvm.lifetime.start.p0i8(i64 32, i8* %1)
13 call void @llvm.lifetime.end.p0i8(i64 32, i8* %1)
21 ; CHECK: [[B:%.*]] = add i64 0, [[A]]
24 …: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_a…
26 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
29 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
32 %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.000000e+00)
39 ; CHECK: store i32 0, i32* bitcast ([100 x i64]* @__msan_va_arg_tls to i32*), align 8
40 ; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64)…
[all …]
|
| /external/llvm-project/llvm/test/Instrumentation/AddressSanitizer/ |
| D | odr-check-ignore.ll | 6 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
14 …i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [56 x i8] }* @a to i64), i64…
15 …i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [56 x i8] }* @b to i64), i64…
16 …i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [56 x i8] }* @c to i64), i64…
17 …i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [56 x i8] }* @d to i64), i64…
19 …i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [56 x i8] }* @0 to i64), i64…
20 …i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [56 x i8] }* @1 to i64), i64…
21 …i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [56 x i8] }* @2 to i64), i64…
22 …i64, i64, i64, i64, i64, i64, i64, i64 } { i64 ptrtoint ({ [2 x i32], [56 x i8] }* @3 to i64), i64…
|
| /external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/ |
| D | stores_vectorize.ll | 16 define void @_Z8DistanceIlLi5EEvPfiPmS0_(float* %p1, i32 %p2, i64* %p3, float* %p4) {
19 ; CHECK-NEXT: store i64 5, i64* [[P3:%.*]], align 8
20 ; CHECK-NEXT: [[IDX_EXT:%.*]] = sext i32 [[P2:%.*]] to i64
21 ; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds float, float* [[P1:%.*]], i64 [[IDX_EXT]]
22 ; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[ADD_PTR]], i64 5
24 ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[P4:%.*]], i64 3
28 ; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i64, i64* [[P3]], i64 1
29 ; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i64, i64* [[P3]], i64 2
30 ; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i64, i64* [[P3]], i64 3
31 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64* [[P3]] to <4 x i64>*
[all …]
|
| /external/llvm/test/CodeGen/SystemZ/ |
| D | bswap-03.ll | 5 declare i64 @llvm.bswap.i64(i64 %a)
8 define i64 @f1(i64 *%src) {
12 %a = load i64 , i64 *%src
13 %swapped = call i64 @llvm.bswap.i64(i64 %a)
14 ret i64 %swapped
18 define i64 @f2(i64 *%src) {
22 %ptr = getelementptr i64, i64 *%src, i64 65535
23 %a = load i64 , i64 *%ptr
24 %swapped = call i64 @llvm.bswap.i64(i64 %a)
25 ret i64 %swapped
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | schedule-kernel-arg-loads.ll | 24 define amdgpu_kernel void @same_base_ptr_crash(i64 addrspace(1)* %out,
25 i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6, i64 %arg7,
26 i64 %arg8, i64 %arg9, i64 %arg10, i64 %arg11, i64 %arg12, i64 %arg13, i64 %arg14, i64 %arg15,
27 i64 %arg16, i64 %arg17, i64 %arg18, i64 %arg19, i64 %arg20, i64 %arg21, i64 %arg22, i64 %arg23,
28 i64 %arg24, i64 %arg25, i64 %arg26, i64 %arg27, i64 %arg28, i64 %arg29, i64 %arg30, i64 %arg31,
29 i64 %arg32, i64 %arg33, i64 %arg34, i64 %arg35, i64 %arg36, i64 %arg37, i64 %arg38, i64 %arg39,
30 i64 %arg40, i64 %arg41, i64 %arg42, i64 %arg43, i64 %arg44, i64 %arg45, i64 %arg46, i64 %arg47,
31 i64 %arg48, i64 %arg49, i64 %arg50, i64 %arg51, i64 %arg52, i64 %arg53, i64 %arg54, i64 %arg55,
32 i64 %arg56, i64 %arg57, i64 %arg58, i64 %arg59, i64 %arg60, i64 %arg61, i64 %arg62, i64 %arg63,
33 i64 %arg64, i64 %arg65, i64 %arg66, i64 %arg67, i64 %arg68, i64 %arg69, i64 %arg70, i64 %arg71,
[all …]
|
| D | flat_atomics_i64.ll | 6 define amdgpu_kernel void @atomic_add_i64_offset(i64* %out, i64 %in) {
8 %gep = getelementptr i64, i64* %out, i64 4
9 %tmp0 = atomicrmw volatile add i64* %gep, i64 %in seq_cst
16 define amdgpu_kernel void @atomic_add_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
18 %gep = getelementptr i64, i64* %out, i64 4
19 %tmp0 = atomicrmw volatile add i64* %gep, i64 %in seq_cst
20 store i64 %tmp0, i64* %out2
26 define amdgpu_kernel void @atomic_add_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
28 %ptr = getelementptr i64, i64* %out, i64 %index
29 %gep = getelementptr i64, i64* %ptr, i64 4
[all …]
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | flat_atomics_i64.ll | 6 define void @atomic_add_i64_offset(i64 addrspace(4)* %out, i64 %in) {
8 %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4
9 %tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst
16 define void @atomic_add_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) {
18 %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4
19 %tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst
20 store i64 %tmp0, i64 addrspace(4)* %out2
26 define void @atomic_add_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) {
28 %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index
29 %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4
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| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | int-sadd-09.ll | 5 declare i64 @foo()
8 define zeroext i1 @f1(i64 *%ptr) {
15 %a = load i64, i64 *%ptr
16 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 1)
17 %val = extractvalue {i64, i1} %t, 0
18 %obit = extractvalue {i64, i1} %t, 1
19 store i64 %val, i64 *%ptr
24 define zeroext i1 @f2(i64 *%ptr) {
31 %a = load i64, i64 *%ptr
32 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %a, i64 127)
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| D | int-ssub-09.ll | 5 declare i64 @foo()
8 define zeroext i1 @f1(i64 *%ptr) {
15 %a = load i64, i64 *%ptr
16 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 1)
17 %val = extractvalue {i64, i1} %t, 0
18 %obit = extractvalue {i64, i1} %t, 1
19 store i64 %val, i64 *%ptr
24 define zeroext i1 @f2(i64 *%ptr) {
31 %a = load i64, i64 *%ptr
32 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 128)
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