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Searched refs:imask (Results 1 – 12 of 12) sorted by relevance

/external/ethtool/
Dfec_8xx.c23 uint32_t imask; /* interrupt mask register */ member
67 DUMP_REG(f, imask); in fec_8xx_dump_regs()
/external/llvm/test/CodeGen/X86/
Davx512-intel-ocl.ll93 %imask = bitcast i16 %mask to <16 x i1>
94 %1 = call intel_ocl_bicc <16 x float> @func_float16_mask(<16 x float> %a, <16 x i1> %imask)
Dmasked_gather_scatter.ll64 ; SCALAR-NEXT: %Mask1 = extractelement <16 x i1> %imask, i32 1
96 %imask = bitcast i16 %mask to <16 x i1>
97 …> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> %imask, <16 x float>undef)
129 %imask = bitcast i16 %mask to <16 x i1>
130 … i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>undef)
171 %imask = bitcast i16 %mask to <16 x i1>
172 … i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>undef)
173 …x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>%gt1)
180 ; SCALAR: %Mask0 = extractelement <16 x i1> %imask, i32 0
189 ; SCALAR-NEXT: %Mask1 = extractelement <16 x i1> %imask, i32 1
[all …]
/external/llvm-project/llvm/docs/AMDGPU/
Dgfx9_imask.rst10 imask title
Dgfx8_imask.rst10 imask title
DAMDGPUAsmGFX8.rst597 …s_set_gpr_idx_on :ref:`ssrc<amdgpu_synid8_ssrc32_0>`, :ref:`imask<amdgpu_synid8_…
655 s_set_gpr_idx_mode :ref:`imask<amdgpu_synid8_imask>`
DAMDGPUAsmGFX9.rst769 …s_set_gpr_idx_on :ref:`ssrc<amdgpu_synid9_ssrc32_0>`, :ref:`imask<amdgpu_synid9_…
829 s_set_gpr_idx_mode :ref:`imask<amdgpu_synid9_imask>`
/external/llvm/test/Analysis/CostModel/X86/
Dmasked-intrinsic-cost.ll206 %imask = bitcast i16 %mask to <16 x i1>
207 … void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
279 …re void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32, <16 x i1> %imask)
/external/llvm-project/llvm/test/CodeGen/X86/
Dmasked_gather_scatter.ll113 %imask = bitcast i16 %mask to <16 x i1>
114 …asked.gather.v16f32.v16p0f32(<16 x float*> %gep.random, i32 4, <16 x i1> %imask, <16 x float>undef)
154 %imask = bitcast i16 %mask to <16 x i1>
155 …vm.masked.gather.v16i32.v16p0i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>undef)
207 %imask = bitcast i16 %mask to <16 x i1>
208 …vm.masked.gather.v16i32.v16p0i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>undef)
209 …lvm.masked.gather.v16i32.v16p0i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>%gt1)
272 %imask = bitcast i16 %mask to <16 x i1>
273 …vm.masked.scatter.v16i32.v16p0i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
274 …vm.masked.scatter.v16i32.v16p0i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
[all …]
Davx512-intel-ocl.ll477 %imask = bitcast i16 %mask to <16 x i1>
478 %1 = call intel_ocl_bicc <16 x float> @func_float16_mask(<16 x float> %a, <16 x i1> %imask)
/external/mesa3d/src/amd/compiler/
Daco_lower_to_hw_instr.cpp1661 uint32_t imask = get_intersection_mask(swap.def.physReg().reg_b, swap.bytes, in handle_operands() local
1664 if (!imask) in handle_operands()
1710 bytes_left &= ~imask; in handle_operands()
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dmasked-intrinsic-cost.ll1534 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask …
1535 …m.masked.scatter.v16i32.v16p0i32(<16 x i32> %val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
1542 ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask…
1543 …m.masked.scatter.v16i32.v16p0i32(<16 x i32> %val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
1550 ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask …
1551 …m.masked.scatter.v16i32.v16p0i32(<16 x i32> %val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
1558 ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask …
1559 …m.masked.scatter.v16i32.v16p0i32(<16 x i32> %val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
1566 ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask t…
1567 …m.masked.scatter.v16i32.v16p0i32(<16 x i32> %val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
[all …]