| /external/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| D | EmulateInstructionARM.cpp | 1151 (result, carry, overflow) = AddWithCarry(SP, imm32, '0'); in EmulateADDRdSPImm()
1171 uint32_t imm32; in EmulateADDRdSPImm() local
1175 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32) in EmulateADDRdSPImm()
1179 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12) in EmulateADDRdSPImm()
1184 addr_t sp_offset = imm32; in EmulateADDRdSPImm()
1365 result = imm32; in EmulateMOVRdImm()
1380 uint32_t imm32; // the immediate value to be written to Rd in EmulateMOVRdImm() local
1390 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32) in EmulateMOVRdImm()
1398 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry); in EmulateMOVRdImm()
1413 imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8; in EmulateMOVRdImm()
[all …]
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| /external/llvm-project/lldb/source/Plugins/Process/Utility/ |
| D | ARMUtils.h | 281 uint32_t imm32; // the expanded result in ARMExpandImm_C() local
285 imm32 = imm; in ARMExpandImm_C()
288 imm32 = ror(imm, 32, amt); in ARMExpandImm_C()
289 carry_out = Bit32(imm32, 31); in ARMExpandImm_C()
291 return imm32; in ARMExpandImm_C()
305 uint32_t imm32; // the expanded result in ThumbExpandImm_C() local
315 imm32 = abcdefgh; in ThumbExpandImm_C()
319 imm32 = abcdefgh << 16 | abcdefgh; in ThumbExpandImm_C()
323 imm32 = abcdefgh << 24 | abcdefgh << 8; in ThumbExpandImm_C()
327 imm32 = abcdefgh << 24 | abcdefgh << 16 | abcdefgh << 8 | abcdefgh; in ThumbExpandImm_C()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/ |
| D | VEInstrFormats.td | 36 bits<32> imm32 = 0;
44 let Inst{63-32} = imm32;
52 let imm32{0-23} = 0;
53 let imm32{24} = cw;
54 let imm32{25} = cw2;
55 let imm32{26-27} = 0;
56 let imm32{28-31} = cfw;
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| D | VEInstrInfo.td | 116 opc, (outs RC:$sx), (ins RC:$sy, RC:$sz, immOp2:$imm32),
117 !strconcat(opcStr, " $sx, ${imm32}($sy, ${sz})")> {
123 opc, (outs RC:$sx), (ins immOp2:$imm32),
124 !strconcat(opcStr, " $sx, $imm32")> {
191 (ins CCOp:$cf, RC:$sy, RC:$sz, brtarget32:$imm32),
192 !strconcat(opcStr, " $sy, $sz, $imm32")> {
224 // As 1st step, only uses sz and imm32 to represent $addr
244 cz = 1, sz = 0x10 /* SX10 */, imm32 = 0, Uses = [SX10],
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| /external/google-breakpad/src/tools/windows/converter_exe/ |
| D | missing_symbols_test.txt | 2 imm32.pdb|98F27BA5AEE541ECBEE00CD03AD50FEE2|6.1.7600.16385|imm32.dll|4A5BDF402e000
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| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEInstrFormats.td | 64 // RM type has sx, sy, sz, and imm32.
65 // The effective address is generated by sz + sy + imm32.
76 bits<32> imm32;
84 let Inst{31-0} = imm32;
91 // by sz + imm32. The sy field is used by other purposes.
125 bits<32> imm32;
135 let Inst{31-0} = imm32;
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| /external/google-breakpad/src/processor/testdata/ |
| D | minidump2.stackwalk.machine_readable.out | 7 Module|imm32.dll|5.1.2600.2180|imm32.pdb|2C17A49C251B4C8EB9E2AD13D7D9EA162|0x76390000|0x763acfff|0
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| D | minidump2.stackwalk.out | 32 0x76390000 - 0x763acfff imm32.dll 5.1.2600.2180
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| /external/igt-gpu-tools/assembler/ |
| D | gram.y | 450 imm32_t imm32; member
562 %type <imm32> imm32
825 $$.reloc.first_reloc_offset = $3.imm32;
832 $3.imm32 |= (1 << 16);
842 $$.reloc.first_reloc_offset = $3.imm32;
848 $$.reloc.first_reloc_offset = $3.imm32;
874 $$.reloc.first_reloc_offset = $4.imm32;
887 $$.reloc.first_reloc_offset = $4.imm32;
889 $$.reloc.second_reloc_offset = $5.imm32;
910 $$.reloc.first_reloc_offset = $4.imm32;
[all …]
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| D | gen4asm.h | 117 uint32_t imm32; /* set if src_operand is expressing a branch offset */ member
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| /external/llvm-project/llvm/docs/AMDGPU/ |
| D | gfx10_bimm32.rst | 10 imm32 title
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| D | gfx9_bimm32.rst | 10 imm32 title
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| D | gfx7_bimm32.rst | 10 imm32 title
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| D | gfx8_bimm32.rst | 10 imm32 title
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| D | gfx10_fimm16.rst | 10 imm32 title
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| D | gfx8_fimm16.rst | 10 imm32 title
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| D | gfx9_fimm16.rst | 10 imm32 title
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| D | gfx9_fimm32.rst | 10 imm32 title
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| D | gfx8_fimm32.rst | 10 imm32 title
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| D | gfx10_fimm32.rst | 10 imm32 title
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| D | gfx7_fimm32.rst | 10 imm32 title
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| /external/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 19 def imm32 : RTLNode;
115 def XOR32mi : Inst<(ops addr:$addr, imm32:$imm),
118 (set R32:$tmp2, (xor R32:$tmp1, imm32:$imm)),
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| /external/llvm-project/llvm/test/TableGen/ |
| D | TargetInstrInfo.td | 19 def imm32 : RTLNode;
115 def XOR32mi : Inst<(ops addr:$addr, imm32:$imm),
118 (set R32:$tmp2, (xor R32:$tmp1, imm32:$imm)),
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.cc | 1268 static inline bool CanBeInverted(uint32_t imm32) { in CanBeInverted() argument
1271 if ((imm32 & 0xffffff00) == 0xffffff00) { in CanBeInverted()
1275 if (((imm32 & 0xff) == 0) || ((imm32 & 0xff) == 0xff)) { in CanBeInverted()
1276 fill8 = imm32 & 0xff; in CanBeInverted()
1277 imm32 >>= 8; in CanBeInverted()
1278 if ((imm32 >> 8) == 0xffff) { in CanBeInverted()
1283 if ((imm32 & 0xff) == fill8) { in CanBeInverted()
1284 imm32 >>= 8; in CanBeInverted()
1285 if ((imm32 >> 8) == 0xff) { in CanBeInverted()
1290 if ((fill8 == 0xff) && ((imm32 & 0xff) == 0xff)) { in CanBeInverted()
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| /external/mesa3d/src/panfrost/bifrost/ |
| D | disassemble.c | 254 uint32_t imm32[2] = { (uint32_t) imm, (uint32_t) (imm >> 32) }; in dump_pc_imm() local
255 uint32_t zx32[2] = { imm32[0] << 4, imm32[1] << 4 }; in dump_pc_imm()
|