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Searched refs:imm6 (Results 1 – 25 of 36) sorted by relevance

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/external/vixl/src/aarch32/
Ddisasm-aarch32.cc31185 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local
31189 imm6; in DecodeT32()
31215 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local
31219 imm6; in DecodeT32()
31245 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local
31249 imm6; in DecodeT32()
31275 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local
31279 imm6; in DecodeT32()
31464 uint32_t imm6 = (instr >> 16) & 0x3f; in DecodeT32() local
31468 imm6; in DecodeT32()
[all …]
Dassembler-aarch32.cc23306 uint32_t imm6 = dt.GetSize() / 2 - imm; in vqrshrn() local
23310 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqrshrn()
23329 uint32_t imm6 = dt.GetSize() / 2 - imm; in vqrshrn() local
23332 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqrshrn()
23358 uint32_t imm6 = dt.GetSize() / 2 - imm; in vqrshrun() local
23361 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqrshrun()
23379 uint32_t imm6 = dt.GetSize() / 2 - imm; in vqrshrun() local
23382 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqrshrun()
23442 uint32_t imm6 = imm; in vqshl() local
23446 rd.Encode(22, 12) | rm.Encode(5, 0) | (imm6 << 16)); in vqshl()
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-basic-a64-undefined.txt16 # ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'.
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Darm64-basic-a64-undefined.txt16 # ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'.
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dconstants-i64.ll242 define i64 @imm6() #0 {
243 ; CHECK-LABEL: imm6:
/external/llvm-project/lld/ELF/Arch/
DRISCV.cpp295 uint16_t imm6 = extractBits(val, 6, 6) << 7; in relocate() local
299 insn |= imm11 | imm4 | imm9_8 | imm10 | imm6 | imm7 | imm3_1 | imm5; in relocate()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td3884 let Inst{21-19} = 0b001; // imm6 = 001xxx
3888 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3892 let Inst{21} = 0b1; // imm6 = 1xxxxx
3896 // imm6 = xxxxxx
3901 let Inst{21-19} = 0b001; // imm6 = 001xxx
3905 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3909 let Inst{21} = 0b1; // imm6 = 1xxxxx
3913 // imm6 = xxxxxx
3921 let Inst{21-19} = 0b001; // imm6 = 001xxx
3925 let Inst{21-20} = 0b01; // imm6 = 01xxxx
[all …]
DARMInstrFormats.td217 // other shift immediates. The imm6 field is encoded like so:
220 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
221 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
222 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
223 // 64 64 - <imm> is encoded in imm6<5:0>
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrNEON.td3952 let Inst{21-19} = 0b001; // imm6 = 001xxx
3956 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3960 let Inst{21} = 0b1; // imm6 = 1xxxxx
3964 // imm6 = xxxxxx
3969 let Inst{21-19} = 0b001; // imm6 = 001xxx
3973 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3977 let Inst{21} = 0b1; // imm6 = 1xxxxx
3981 // imm6 = xxxxxx
3989 let Inst{21-19} = 0b001; // imm6 = 001xxx
3993 let Inst{21-20} = 0b01; // imm6 = 01xxxx
[all …]
DARMInstrFormats.td309 // other shift immediates. The imm6 field is encoded like so:
312 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
313 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
314 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
315 // 64 64 - <imm> is encoded in imm6<5:0>
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td4021 let Inst{21-19} = 0b001; // imm6 = 001xxx
4025 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4029 let Inst{21} = 0b1; // imm6 = 1xxxxx
4033 // imm6 = xxxxxx
4038 let Inst{21-19} = 0b001; // imm6 = 001xxx
4042 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4046 let Inst{21} = 0b1; // imm6 = 1xxxxx
4050 // imm6 = xxxxxx
4058 let Inst{21-19} = 0b001; // imm6 = 001xxx
4062 let Inst{21-20} = 0b01; // imm6 = 01xxxx
[all …]
DARMInstrFormats.td310 // other shift immediates. The imm6 field is encoded like so:
313 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
314 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
315 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
316 // 64 64 - <imm> is encoded in imm6<5:0>
DARMInstrMVE.td3428 (outs MQPR:$Qd), (ins MQPR:$Qm, imm_operand_type:$imm6),
3429 "$Qd, $Qm, $imm6", vpred_r, "", pattern> {
3431 bits<6> imm6;
3437 let Inst{19-16} = imm6{3-0};
3464 let Inst{20} = imm6{4};
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DSVEInstrFormats.td1991 : I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),
1992 asm, "\t$Rd, $Rn, $imm6",
1997 bits<6> imm6;
2003 let Inst{10-5} = imm6;
2008 : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
2009 asm, "\t$Rd, $imm6",
2013 bits<6> imm6;
2019 let Inst{10-5} = imm6;
5697 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6),
5698 asm, "\t$Zt, $Pg/z, [$Rn, $imm6]",
[all …]
DAArch64InstrFormats.td850 // {5-0} - imm6
880 // {5-0} - imm6
910 // {5-0} - imm6: #0, #8, #16, or #24
919 // {5-0} - imm6: #0 or #8
949 // {5-0} - imm6: #0 or #12
2473 isSub, 0, GPR64sp, asm_inst, "\t$Rd, $Rn, $imm6, $imm4",
2474 (ins GPR64sp:$Rn, uimm6s16:$imm6, imm0_15:$imm4),
2475 (set GPR64sp:$Rd, (OpNode GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4))> {
2476 bits<6> imm6;
2480 let Inst{21-16} = imm6;
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt357 # imm6=0b0xxxxx -> UNDEFINED
/external/vixl/src/aarch64/
Dassembler-sve-aarch64.cc4516 int64_t imm6 = addr.GetImmediateOffset(); in SVEGatherPrefetchScalarPlusImmediateHelper() local
4538 RnSP(addr.GetScalarBase()) | ImmField<21, 16>(imm6)); in SVEGatherPrefetchScalarPlusImmediateHelper()
6281 void Assembler::addpl(const Register& xd, const Register& xn, int imm6) { in addpl() argument
6290 Emit(ADDPL_r_ri | RdSP(xd) | RmSP(xn) | ImmField<10, 5>(imm6)); in addpl()
6293 void Assembler::addvl(const Register& xd, const Register& xn, int imm6) { in addvl() argument
6302 Emit(ADDVL_r_ri | RdSP(xd) | RmSP(xn) | ImmField<10, 5>(imm6)); in addvl()
6307 void Assembler::rdvl(const Register& xd, int imm6) { in rdvl() argument
6315 Emit(RDVL_r_i | Rd(xd) | ImmField<10, 5>(imm6)); in rdvl()
Dassembler-aarch64.h3607 void addpl(const Register& xd, const Register& xn, int imm6);
3610 void addvl(const Register& xd, const Register& xn, int imm6);
5168 void rdvl(const Register& xd, int imm6);
6178 static Instr ImmRMIFRotation(int imm6) { in ImmRMIFRotation() argument
6179 VIXL_ASSERT(IsUint6(imm6)); in ImmRMIFRotation()
6180 return imm6 << ImmRMIFRotation_offset; in ImmRMIFRotation()
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt380 # imm6=0b0xxxxx -> UNDEFINED
/external/llvm-project/llvm/lib/Target/AArch64/
DSVEInstrFormats.td2187 : I<(outs GPR64sp:$Rd), (ins GPR64sp:$Rn, simm6_32b:$imm6),
2188 asm, "\t$Rd, $Rn, $imm6",
2193 bits<6> imm6;
2199 let Inst{10-5} = imm6;
2204 : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
2205 asm, "\t$Rd, $imm6",
2209 bits<6> imm6;
2215 let Inst{10-5} = imm6;
6311 : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6),
6312 asm, "\t$Zt, $Pg/z, [$Rn, $imm6]",
[all …]
DAArch64InstrFormats.td954 // {5-0} - imm6
984 // {5-0} - imm6
1014 // {5-0} - imm6: #0, #8, #16, or #24
1023 // {5-0} - imm6: #0 or #8
1053 // {5-0} - imm6: #0 or #12
2609 isSub, 0, GPR64sp, asm_inst, "\t$Rd, $Rn, $imm6, $imm4",
2610 (ins GPR64sp:$Rn, uimm6s16:$imm6, imm0_15:$imm4),
2611 (set GPR64sp:$Rd, (OpNode GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4))> {
2612 bits<6> imm6;
2616 let Inst{21-16} = imm6;
/external/skia/src/core/
DSkVM.h331 void add (X d, X n, X m, Shift=LSL, int imm6=0); // d=n+Shift(m,imm6), for Shift != ROR.
/external/llvm/lib/Target/AVR/
DAVRInstrInfo.td183 // Addressing mode pattern reg+imm6
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRInstrInfo.td225 // Addressing mode pattern reg+imm6
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td574 // {5-0} - imm6
596 // {5-0} - imm6
618 // {5-0} - imm6: #0, #8, #16, or #24
627 // {5-0} - imm6: #0 or #8
655 // {5-0} - imm6: #0 or #12

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