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Searched refs:ineg (Results 1 – 25 of 79) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinst-select-abs.mir27 %ineg:sgpr(s32) = G_SUB %zero, %src0
28 %smax:sgpr(s32) = G_SMAX %src0, %ineg
54 %ineg:sgpr(s32) = G_SUB %zero, %src0
55 %smax:sgpr(s32) = G_SMAX %ineg, %src0
73 ; GFX6: %ineg:vgpr_32, dead %4:sreg_64_xexec = V_SUB_CO_U32_e64 %zero, %src0, 0, implicit $exec
74 ; GFX6: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec
80 ; GFX9: %ineg:vgpr_32 = V_SUB_U32_e64 %zero, %src0, 0, implicit $exec
81 ; GFX9: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec
85 %ineg:vgpr(s32) = G_SUB %zero, %src0
86 %smax:vgpr(s32) = G_SMAX %src0, %ineg
[all …]
/external/pdfium/core/fxcrt/
Dfx_memory_unittest.cpp113 int ineg = -513; in TEST() local
117 EXPECT_EQ(-512, FxAlignToBoundary<512>(ineg)); in TEST()
/external/deqp-deps/glslang/Test/
Dspv.intcoopmat.comp43 icoopmatNV<8, gl_ScopeSubgroup, 8, 8> ineg(icoopmatNV<8, gl_ScopeSubgroup, 8, 8> m) { return -m; }
104 p1 = ineg(p1);
/external/deqp-deps/glslang/Test/baseResults/
Dspv.intcoopmat.comp.out29 Name 14 "ineg(i81;"
375 191: 10 FunctionCall 14(ineg(i81;) 189(param)
405 14(ineg(i81;): 10 Function None 12
/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_compiler_nir_emit.c91 IOP(ineg, ADD, X_X_0), /* ADD 0, -x */
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td379 [(set GR8:$dst, (ineg GR8:$src1)),
383 [(set GR16:$dst, (ineg GR16:$src1)),
387 [(set GR32:$dst, (ineg GR32:$src1)),
390 [(set GR64:$dst, (ineg GR64:$src1)),
398 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
402 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
406 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
409 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
DX86InstrCompiler.td960 (ineg (atomic_load_8 addr:$dst)),
961 (ineg (atomic_load_16 addr:$dst)),
962 (ineg (atomic_load_32 addr:$dst)),
963 (ineg (atomic_load_64 addr:$dst))>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrArithmetic.td356 [(set GR8:$dst, (ineg GR8:$src1)),
360 [(set GR16:$dst, (ineg GR16:$src1)),
364 [(set GR32:$dst, (ineg GR32:$src1)),
367 [(set GR64:$dst, (ineg GR64:$src1)),
375 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
379 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
383 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
386 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
DX86InstrCompiler.td1059 (ineg (i8 (atomic_load_8 addr:$dst))),
1060 (ineg (i16 (atomic_load_16 addr:$dst))),
1061 (ineg (i32 (atomic_load_32 addr:$dst))),
1062 (ineg (i64 (atomic_load_64 addr:$dst)))>;
/external/llvm-project/llvm/lib/Target/PowerPC/
DREADME_P9.txt93 . Map to llvm ineg
94 (set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
95 (set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
/external/llvm/lib/Target/PowerPC/
DREADME_P9.txt93 . Map to llvm ineg
94 (set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
95 (set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DREADME_P9.txt93 . Map to llvm ineg
94 (set v4i32:$rT, (ineg v4i32:$rA)) // vnegw
95 (set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
/external/llvm/lib/Target/SystemZ/
DSystemZOperators.td546 def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>;
555 def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>;
556 def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>;
DSystemZInstrInfo.td811 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>;
812 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
817 defm : SXU<ineg, LCGFR>;
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrArithmetic.td356 [(set GR8:$dst, (ineg GR8:$src1)),
360 [(set GR16:$dst, (ineg GR16:$src1)),
364 [(set GR32:$dst, (ineg GR32:$src1)),
367 [(set GR64:$dst, (ineg GR64:$src1)),
375 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
379 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
383 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
386 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
DX86InstrCompiler.td1054 (ineg (i8 (atomic_load_8 addr:$dst))),
1055 (ineg (i16 (atomic_load_16 addr:$dst))),
1056 (ineg (i32 (atomic_load_32 addr:$dst))),
1057 (ineg (i64 (atomic_load_64 addr:$dst)))>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZOperators.td668 def z_inegabs : PatFrag<(ops node:$src), (ineg (z_iabs node:$src))>;
677 def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>;
678 def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>;
/external/swiftshader/src/Shader/
DShaderCore.hpp244 void ineg(Vector4f &dst, const Vector4f &src);
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFInstrInfo.td315 [(set GPR:$dst, (ineg i64:$src))]>;
318 [(set GPR32:$dst, (ineg i32:$src))]>;
/external/llvm-project/llvm/lib/Target/BPF/
DBPFInstrInfo.td315 [(set GPR:$dst, (ineg i64:$src))]>;
318 [(set GPR32:$dst, (ineg i32:$src))]>;
/external/llvm/lib/Target/ARM/
DARMInstrThumb.td994 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
1000 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
1190 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb.td1089 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
1095 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
1285 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb.td1101 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
1107 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
1297 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td726 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
728 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
730 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
732 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
747 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
749 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
760 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))),
762 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))),
764 def : Pat<(i64 (ineg (mul (sext_inreg GPR64:$Rn, i32), (s64imm_32bit:$C)))),
1117 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
/external/llvm-project/llvm/lib/Target/AVR/
DAVRInstrInfo.td740 [(set i8:$rd, (ineg i8:$src)), (implicit SREG)]>;
751 [(set i16:$rd, (ineg i16:$src)), (implicit SREG)]>;

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