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Searched refs:isARMLowRegister (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp77 isARMLowRegister(SrcReg))) && "Unknown regclass!"); in storeRegToStackSlot()
81 isARMLowRegister(SrcReg))) { in storeRegToStackSlot()
103 isARMLowRegister(DestReg))) && "Unknown regclass!"); in loadRegFromStackSlot()
107 isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
DThumb2SizeReduction.cpp371 if (!isARMLowRegister(Reg)) in VerifyLowRegs()
442 assert(isARMLowRegister(Rt)); in ReduceLoadStore()
443 assert(isARMLowRegister(Rn)); in ReduceLoadStore()
470 assert(isARMLowRegister(BaseReg)); in ReduceLoadStore()
517 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()
611 if (!isARMLowRegister(MI->getOperand(0).getReg())) in ReduceSpecial()
712 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
713 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
737 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
746 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
[all …]
DThumbRegisterInfo.cpp110 assert((isARMLowRegister(DestReg) || isVirtualRegister(DestReg)) && in emitLoadConstPool()
129 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
130 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
143 if (!isARMLowRegister(DestReg) && !MRI.isVirtualRegister(DestReg)) in emitThumbRegPlusImmInReg()
223 } else if (isARMLowRegister(DestReg)) { in emitThumbRegPlusImmediate()
233 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
DARMConstantIslandPass.cpp1852 if (isARMLowRegister(U.MI->getOperand(0).getReg())) { in optimizeThumb2Instructions()
1859 if (isARMLowRegister(U.MI->getOperand(0).getReg())) { in optimizeThumb2Instructions()
1966 isARMLowRegister(Reg)) { in optimizeThumb2Branches()
DARMFrameLowering.cpp1673 isARMLowRegister(Reg) || Reg == ARM::LR) { in determineCalleeSaves()
1702 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || in determineCalleeSaves()
DARMLoadStoreOptimizer.cpp701 if (isARMLowRegister(NewBase) && isARMLowRegister(Base) && in CreateLoadStoreMulti()
/external/llvm-project/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp83 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) && in storeRegToStackSlot()
87 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) { in storeRegToStackSlot()
112 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) && in loadRegFromStackSlot()
116 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
DThumb2SizeReduction.cpp397 if (!isARMLowRegister(Reg)) in VerifyLowRegs()
472 assert(isARMLowRegister(Rt)); in ReduceLoadStore()
473 assert(isARMLowRegister(Rn)); in ReduceLoadStore()
500 assert(isARMLowRegister(BaseReg)); in ReduceLoadStore()
556 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()
651 if (!isARMLowRegister(MI->getOperand(0).getReg())) in ReduceSpecial()
762 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
763 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
787 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
796 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
[all …]
DThumbRegisterInfo.cpp110 assert((isARMLowRegister(DestReg) || DestReg.isVirtual()) && in emitLoadConstPool()
130 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
131 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
144 if (!isARMLowRegister(DestReg) && !Register::isVirtualRegister(DestReg)) in emitThumbRegPlusImmInReg()
230 } else if (isARMLowRegister(DestReg)) { in emitThumbRegPlusImmediate()
240 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
DThumb1FrameLowering.cpp381 if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) { in emitPrologue()
536 if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) { in emitEpilogue()
DARMConstantIslandPass.cpp1752 if (isARMLowRegister(U.MI->getOperand(0).getReg())) { in optimizeThumb2Instructions()
1759 if (isARMLowRegister(U.MI->getOperand(0).getReg())) { in optimizeThumb2Instructions()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp83 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) && in storeRegToStackSlot()
87 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) { in storeRegToStackSlot()
112 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) && in loadRegFromStackSlot()
116 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
DThumb2SizeReduction.cpp397 if (!isARMLowRegister(Reg)) in VerifyLowRegs()
472 assert(isARMLowRegister(Rt)); in ReduceLoadStore()
473 assert(isARMLowRegister(Rn)); in ReduceLoadStore()
500 assert(isARMLowRegister(BaseReg)); in ReduceLoadStore()
546 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()
641 if (!isARMLowRegister(MI->getOperand(0).getReg())) in ReduceSpecial()
752 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
753 || !isARMLowRegister(Reg2)) in ReduceTo2Addr()
777 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
786 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) in ReduceTo2Addr()
[all …]
DThumbRegisterInfo.cpp111 (isARMLowRegister(DestReg) || Register::isVirtualRegister(DestReg)) && in emitLoadConstPool()
131 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
132 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
145 if (!isARMLowRegister(DestReg) && !Register::isVirtualRegister(DestReg)) in emitThumbRegPlusImmInReg()
231 } else if (isARMLowRegister(DestReg)) { in emitThumbRegPlusImmediate()
241 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
DThumb1FrameLowering.cpp379 if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) { in emitPrologue()
534 if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) { in emitEpilogue()
DARMConstantIslandPass.cpp1779 if (isARMLowRegister(U.MI->getOperand(0).getReg())) { in optimizeThumb2Instructions()
1786 if (isARMLowRegister(U.MI->getOperand(0).getReg())) { in optimizeThumb2Instructions()
DARMFrameLowering.cpp2057 isARMLowRegister(Reg) || in determineCalleeSaves()
2092 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg))) { in determineCalleeSaves()
DARMLoadStoreOptimizer.cpp736 if (isARMLowRegister(NewBase) && isARMLowRegister(Base) && in CreateLoadStoreMulti()
/external/capstone/arch/ARM/
DARMBaseInfo.h181 static inline bool isARMLowRegister(unsigned Reg) in isARMLowRegister() function
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMBaseInfo.h160 static inline bool isARMLowRegister(unsigned Reg) { in isARMLowRegister() function
/external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
DARMBaseInfo.h160 static inline bool isARMLowRegister(unsigned Reg) { in isARMLowRegister() function
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1281 return isARMLowRegister(Memory.BaseRegNum) && in isMemThumbRR()
1282 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); in isMemThumbRR()
1286 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs4()
1295 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs2()
1304 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs1()
5672 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && in shouldOmitCCOutOperand()
5673 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && in shouldOmitCCOutOperand()
5699 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
5700 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
5701 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || in shouldOmitCCOutOperand()
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMBaseInfo.h210 static inline bool isARMLowRegister(unsigned Reg) { in isARMLowRegister() function
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1637 return isARMLowRegister(Memory.BaseRegNum) && in isMemThumbRR()
1638 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); in isMemThumbRR()
1643 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs4()
1653 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs2()
1663 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs1()
6550 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && in shouldOmitCCOutOperand()
6551 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && in shouldOmitCCOutOperand()
6578 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
6579 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
6580 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || in shouldOmitCCOutOperand()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1703 return isARMLowRegister(Memory.BaseRegNum) && in isMemThumbRR()
1704 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); in isMemThumbRR()
1709 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs4()
1719 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs2()
1729 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) in isMemThumbRIs1()
6645 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && in shouldOmitCCOutOperand()
6646 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && in shouldOmitCCOutOperand()
6673 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
6674 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
6675 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || in shouldOmitCCOutOperand()
[all …]

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