| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 302 let isAllocatable = 0;
307 let isAllocatable = 0;
313 let isAllocatable = 0;
327 let isAllocatable = 0;
368 let isAllocatable = 0;
374 let isAllocatable = 0;
522 let isAllocatable = 0;
565 let isAllocatable = 0;
571 let isAllocatable = 0;
577 let isAllocatable = 0;
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 219 let isAllocatable = 0;
224 let isAllocatable = 0;
261 let isAllocatable = 0;
415 let isAllocatable = 0;
421 let isAllocatable = 0;
427 let isAllocatable = 0;
459 let isAllocatable = 0;
477 let isAllocatable = 0;
495 let isAllocatable = 0;
501 let isAllocatable = 0;
[all …]
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| D | R600RegisterInfo.td | 160 let isAllocatable = 0 in {
206 } // End isAllocatable = 0
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| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 112 if (!RC || RC->isAllocatable()) in getAllocatableClass()
118 if (SubRC->isAllocatable()) in getAllocatableClass()
149 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
166 if ((*I)->isAllocatable()) in getAllocatableSet()
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| D | MachineRegisterInfo.cpp | 40 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); in setRegClass()
97 assert(RegClass->isAllocatable() && in createVirtualRegister()
455 if (!def_empty(*AI) || isAllocatable(*AI)) in isConstantPhysReg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 174 if (!RC || RC->isAllocatable()) in getAllocatableClass()
180 if (SubRC->isAllocatable()) in getAllocatableClass()
211 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
227 if (C->isAllocatable()) in getAllocatableSet()
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| D | MachineRegisterInfo.cpp | 59 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); in setRegClass()
161 assert(RegClass->isAllocatable() && in createVirtualRegister()
530 if (!def_empty(*AI) || isAllocatable(*AI)) in isConstantPhysReg()
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| D | RegAllocFast.cpp | 674 if (Hint0.isPhysical() && MRI->isAllocatable(Hint0) && in allocVirtReg()
695 if (Hint1.isPhysical() && MRI->isAllocatable(Hint1) && in allocVirtReg()
1062 if (!MRI->isAllocatable(Reg)) continue; in allocateInstruction()
1172 if (!Reg || !Reg.isPhysical() || !MRI->isAllocatable(Reg)) in allocateInstruction()
1257 if (MRI->isAllocatable(LI.PhysReg)) in allocateBasicBlock()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 194 if (!RC || RC->isAllocatable()) in getAllocatableClass()
200 if (SubRC->isAllocatable()) in getAllocatableClass()
231 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); in getAllocatableSetForRC()
247 if (C->isAllocatable()) in getAllocatableSet()
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| D | MachineRegisterInfo.cpp | 59 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); in setRegClass()
161 assert(RegClass->isAllocatable() && in createVirtualRegister()
530 if (!def_empty(*AI) || isAllocatable(*AI)) in isConstantPhysReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 361 let Size = 32, isAllocatable = 0 in
368 let isAllocatable = 0 in
371 let Size = 64, isAllocatable = 0 in
376 let Size = 32, isAllocatable = 0 in
386 let Size = 64, isAllocatable = 0 in
397 let isAllocatable = 0 in
403 let Size = 32, isAllocatable = 0 in
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 397 let Size = 32, isAllocatable = 0 in
408 let isAllocatable = 0 in
411 let Size = 64, isAllocatable = 0 in
416 let Size = 32, isAllocatable = 0 in
426 let Size = 64, isAllocatable = 0 in
437 let isAllocatable = 0 in
443 let Size = 32, isAllocatable = 0 in
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 120 let isAllocatable = 0;
177 let isAllocatable = 0;
275 let isAllocatable = 0;
291 let isAllocatable = 0;
|
| D | SIFrameLowering.cpp | 165 assert(MRI.isAllocatable(Reg)); in emitPrologue()
195 if (!MRI.isAllocatable(Reg) || in emitPrologue()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 408 let isAllocatable = 0 in
417 let isAllocatable = 0 in
551 let isAllocatable = 0;
558 let isAllocatable = 0;
575 let isAllocatable = 0;
579 let isAllocatable = 0;
583 let isAllocatable = 0;
636 let isAllocatable = 0 in
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 57 let isAllocatable = 0;
|
| /external/llvm-project/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 57 let isAllocatable = 0;
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.td | 58 let isAllocatable = 0;
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.td | 63 let isAllocatable = 0;
|
| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.td | 62 let isAllocatable = 0;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.td | 62 let isAllocatable = 0;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 398 let isAllocatable = 0 in
407 let isAllocatable = 0 in
541 let isAllocatable = 0;
548 let isAllocatable = 0;
565 let isAllocatable = 0;
569 let isAllocatable = 0;
573 let isAllocatable = 0;
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 120 bool isAllocatable() const { return MC->isAllocatable(); } in isAllocatable() function
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 41 let isAllocatable = allocatable in
295 let isAllocatable = 0, CopyCost = -1 in
302 let isAllocatable = 0 in
|
| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.td | 41 let isAllocatable = allocatable in
295 let isAllocatable = 0, CopyCost = -1 in
302 let isAllocatable = 0 in
|