| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 295 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), in optimizeSDPattern()
341 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass)) in hasPartialWrite()
405 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 287 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), in optimizeSDPattern()
333 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass)) in hasPartialWrite()
397 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 287 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), in optimizeSDPattern()
333 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass)) in hasPartialWrite()
397 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 66 !MI->isRegSequence() && in canTurnIntoImplicitDef()
|
| D | PeepholeOptimizer.cpp | 241 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()
1019 assert(MI.isRegSequence() && "Invalid instruction"); in RegSequenceRewriter()
1880 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()
2065 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
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| D | TargetInstrInfo.cpp | 1216 assert((MI.isRegSequence() || in getRegSequenceInputs()
1219 if (!MI.isRegSequence()) in getRegSequenceInputs()
|
| /external/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 68 !MI->isRegSequence() && in canTurnIntoImplicitDef()
|
| D | PeepholeOptimizer.cpp | 198 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()
1083 assert(MI.isRegSequence() && "Invalid instruction"); in RegSequenceRewriter()
1716 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()
1902 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
|
| D | TargetInstrInfo.cpp | 1126 assert((MI.isRegSequence() || in getRegSequenceInputs()
1129 if (!MI.isRegSequence()) in getRegSequenceInputs()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 66 !MI->isRegSequence() && in canTurnIntoImplicitDef()
|
| D | PeepholeOptimizer.cpp | 244 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()
1024 assert(MI.isRegSequence() && "Invalid instruction"); in RegSequenceRewriter()
1880 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()
2065 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
|
| D | TargetInstrInfo.cpp | 1289 assert((MI.isRegSequence() || in getRegSequenceInputs()
1292 if (!MI.isRegSequence()) in getRegSequenceInputs()
|
| /external/llvm-project/llvm/utils/TableGen/ |
| D | InstrDocsEmitter.cpp | 135 FLAG(isRegSequence) in EmitInstrDocs()
|
| D | CodeGenInstruction.h | 273 bool isRegSequence : 1; variable
|
| D | InstrInfoEmitter.cpp | 780 if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)"; in emitRecord()
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.h | 255 bool isRegSequence : 1; variable
|
| D | InstrInfoEmitter.cpp | 506 if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)"; in emitRecord()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 180 assert(MI.isRegSequence()); in foldVGPRCopyIntoRegSequence()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 244 assert(MI.isRegSequence()); in foldVGPRCopyIntoRegSequence()
774 if (UseMI->isCopy() || UseMI->isRegSequence()) { in processPHINode()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 242 assert(MI.isRegSequence()); in foldVGPRCopyIntoRegSequence()
814 if (UseMI->isCopy() || UseMI->isRegSequence()) { in processPHINode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 469 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
1107 bool isRegSequence() const {
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 555 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
1216 bool isRegSequence() const {
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 346 if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs == 1) { in adjustSchedDependency()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 271 return !MI.isInsertSubreg() && !MI.isSubregToReg() && !MI.isRegSequence(); in shouldSink()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 811 bool isRegSequence() const {
|