| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64PostLegalizerCombiner.cpp | 114 static bool isZeroExtended(Register R, MachineRegisterInfo &MRI) { in isZeroExtended() function
152 (isSignExtended(LHS, MRI) || isZeroExtended(LHS, MRI))) in matchAArch64MulConstCombine()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 417 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
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| D | PPCMIPeephole.cpp | 207 if (TII->isZeroExtended(*MI)) in getKnownLeadingZeroCount()
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| D | PPCInstrInfo.cpp | 1669 if (isZeroExtended(*MI)) { in optimizeCompareInstr()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 581 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
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| D | PPCMIPeephole.cpp | 214 if (TII->isZeroExtended(*MI)) in getKnownLeadingZeroCount()
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| D | PPCInstrInfo.cpp | 1971 if (isZeroExtended(*MI)) { in optimizeCompareInstr()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2181 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() function
2206 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
2226 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
2227 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2826 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() function
2848 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
2888 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
2889 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
9786 isZeroExtended(N0.getNode(), DAG))) in performMulCombine()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 6499 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() function
6630 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
6650 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
6651 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 3382 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() function
3404 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
3454 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
3455 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
11648 isZeroExtended(N0.getNode(), DAG))) in performMulCombine()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 8423 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() function
8564 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
8584 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
8585 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 8729 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { in isZeroExtended() function
8870 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); in isAddSubZExt()
8890 bool isN0ZExt = isZeroExtended(N0, DAG); in LowerMUL()
8891 bool isN1ZExt = isZeroExtended(N1, DAG); in LowerMUL()
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