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Searched refs:ld4d (Results 1 – 21 of 21) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dld4d-diagnostics.s7 ld4d {z12.d, z13.d, z14.d, z15.d}, p4/z, [x12, #-36, MUL VL] label
12 ld4d {z7.d, z8.d, z9.d, z10.d}, p3/z, [x1, #32, MUL VL] label
21 ld4d {z12.d, z13.d, z14.d, z15.d}, p4/z, [x12, #-7, MUL VL] label
26 ld4d {z7.d, z8.d, z9.d, z10.d}, p3/z, [x1, #5, MUL VL] label
35 ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0] label
40 ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, xzr] label
45 ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #2] label
50 ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0] label
55 ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, w0, uxtw] label
64 ld4d {z2.d, z3.d, z4.d, z5.d}, p8/z, [x15, #10, MUL VL] label
[all …]
Dld4d.s10 ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3] label
16 ld4d { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3] label
22 ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0] label
28 ld4d { z23.d, z24.d, z25.d, z26.d }, p3/z, [x13, #-32, mul vl] label
34 ld4d { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl] label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-calling-convention-mixed.ll15 ; CHECK-NEXT: ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]
16 ; CHECK-NEXT: ld4d { z16.d, z17.d, z18.d, z19.d }, p0/z, [x1]
47 ; CHECK-NEXT: ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]
48 ; CHECK-NEXT: ld4d { z16.d, z17.d, z18.d, z19.d }, p0/z, [x1]
86 ; CHECK-NEXT: ld4d { z2.d, z3.d, z4.d, z5.d }, p0/z, [x0]
Dsve-intrinsics-ldN-reg+reg-addr-mode.ll216 ; ld4d
219 ; CHECK: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x1, lsl #3]
228 ; CHECK: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x1, lsl #3]
Dsve-intrinsics-ldN-reg+imm-addr-mode.ll450 ; ld4d
453 ; CHECK: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, #28, mul vl]
463 ; CHECK: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, #-32, mul vl]
Dsve-intrinsics-loads.ll511 ; CHECK: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
519 ; CHECK: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc4138 COMPARE_PREFIX(ld4d(z0.VnD(), in TEST()
4145 COMPARE_PREFIX(ld4d(z0.VnD(), in TEST()
4152 COMPARE_PREFIX(ld4d(z0.VnD(), in TEST()
4386 COMPARE_PREFIX(ld4d(z16.VnD(), in TEST()
4394 COMPARE_PREFIX(ld4d(z16.VnD(), in TEST()
4402 COMPARE_PREFIX(ld4d(z25.VnD(), in TEST()
Dtest-trace-aarch64.cc2876 __ ld4d(z28.VnD(), in GenerateTestSequenceSVE() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td453 defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4s4>;
467 def LD4D : sve_mem_eld_ss<0b11, 0b11, ZZZZ_d, "ld4d", GPR64NoXZRshifted64>;
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td793 defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4s4>;
807 def LD4D : sve_mem_eld_ss<0b11, 0b11, ZZZZ_d, "ld4d", GPR64NoXZRshifted64>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12517 "ld4b\004ld4d\004ld4h\004ld4r\004ld4w\005ldadd\006ldadda\007ldaddab\007l"
15691 …{ 2041 /* ld4d */, AArch64::LD4D_IMM, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_…
15692 …{ 2041 /* ld4d */, AArch64::LD4D, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__G…
15693 …{ 2041 /* ld4d */, AArch64::LD4D_IMM, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_…
23064 …{ 2041 /* ld4d */, AArch64::LD4D_IMM, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_…
23065 …{ 2041 /* ld4d */, AArch64::LD4D, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__G…
23066 …{ 2041 /* ld4d */, AArch64::LD4D_IMM, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_…
32881 { 2041 /* ld4d */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
32882 { 2041 /* ld4d */, 1 /* 0 */, MCK_SVEVectorList464, AMFBS_HasSVE },
32883 { 2041 /* ld4d */, 2 /* 1 */, MCK_SVEPredicate3bAnyReg, AMFBS_HasSVE },
[all …]
DAArch64GenAsmWriter.inc22402 /* 5586 */ "ld4d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
DAArch64GenAsmWriter1.inc23123 /* 5578 */ "ld4d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0"
/external/vixl/src/aarch64/
Dassembler-aarch64.h4696 void ld4d(const ZRegister& zt1,
Dmacro-assembler-aarch64.h5010 ld4d(zt1, zt2, zt3, zt4, pg, addr); in Ld4d()
/external/vixl/test/test-trace-reference/
Dlog-disasm2452 0x~~~~~~~~~~~~~~~~ a5e1f41c ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl]
Dlog-disasm-colour2452 0x~~~~~~~~~~~~~~~~ a5e1f41c ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl]
Dlog-cpufeatures-custom2451 0x~~~~~~~~~~~~~~~~ a5e1f41c ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl] ### {SVE} …
Dlog-cpufeatures2451 0x~~~~~~~~~~~~~~~~ a5e1f41c ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl] // Needs: …
Dlog-cpufeatures-colour2451 0x~~~~~~~~~~~~~~~~ a5e1f41c ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl] SVE…
Dlog-all11829 0x~~~~~~~~~~~~~~~~ a5e1f41c ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl]