| /external/llvm/test/MC/AArch64/ |
| D | armv8.1a-lor.s | 10 ldlar w0,[x1]
11 ldlar x0,[x1]
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | armv8.1a-lor.s | 10 ldlar w0,[x1]
11 ldlar x0,[x1]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-lor.txt | 13 # CHECK: ldlar w0, [x1]
14 # CHECK: ldlar x0, [x1]
|
| /external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-lor.txt | 13 # CHECK: ldlar w0, [x1]
14 # CHECK: ldlar x0, [x1]
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 1663 COMPARE(ldlar(w24, MemOperand(x25)), "ldlar w24, [x25]"); in TEST()
1664 COMPARE(ldlar(w26, MemOperand(sp)), "ldlar w26, [sp]"); in TEST()
1665 COMPARE(ldlar(x27, MemOperand(x28)), "ldlar x27, [x28]"); in TEST()
1666 COMPARE(ldlar(x29, MemOperand(sp)), "ldlar x29, [sp]"); in TEST()
|
| D | test-cpu-features-aarch64.cc | 3519 TEST_LOREGIONS(ldlar_0, ldlar(w0, MemOperand(x1, 0)))
3520 TEST_LOREGIONS(ldlar_1, ldlar(x0, MemOperand(x1, 0)))
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 1384 void ldlar(const Register& rt, const MemOperand& src);
|
| D | assembler-aarch64.cc | 1634 void Assembler::ldlar(const Register& rt, const MemOperand& src) { in ldlar() function in vixl::aarch64::Assembler
|
| D | macro-assembler-aarch64.h | 1712 ldlar(rt, src); in Ldlar()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2477 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
2478 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1231 void ldlar(const Register& rt, const MemOperand& src)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3286 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
3287 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3492 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
3493 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12526 "f1sw\006ldff1w\003ldg\004ldgm\005ldlar\006ldlarb\006ldlarh\006ldnf1b\006"
16047 …{ 2511 /* ldlar */, AArch64::LDLARW, Convert__Reg1_0__GPR64sp01_2, AMFBS_HasLOR, { MCK_GPR32, MCK_…
16048 …{ 2511 /* ldlar */, AArch64::LDLARX, Convert__Reg1_0__GPR64sp01_2, AMFBS_HasLOR, { MCK_GPR64, MCK_…
23420 …{ 2511 /* ldlar */, AArch64::LDLARW, Convert__Reg1_0__GPR64sp01_2, AMFBS_HasLOR, { MCK_GPR32, MCK_…
23421 …{ 2511 /* ldlar */, AArch64::LDLARX, Convert__Reg1_0__GPR64sp01_2, AMFBS_HasLOR, { MCK_GPR64, MCK_…
34135 { 2511 /* ldlar */, 4 /* 2 */, MCK_GPR64sp0, AMFBS_HasLOR },
34136 { 2511 /* ldlar */, 4 /* 2 */, MCK_GPR64sp0, AMFBS_HasLOR },
34137 { 2511 /* ldlar */, 4 /* 2 */, MCK_GPR64sp0, AMFBS_HasLOR },
34138 { 2511 /* ldlar */, 4 /* 2 */, MCK_GPR64sp0, AMFBS_HasLOR },
|