Home
last modified time | relevance | path

Searched refs:ldxr (Results 1 – 25 of 55) sorted by relevance

123

/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64_32-atomics.ll74 declare i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
75 declare i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
76 declare i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
77 declare i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
83 %val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
92 %val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
99 ; CHECK: ldxr w0, [x0]
101 %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
108 ; CHECK: ldxr x0, [x0]
110 %val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
Darm64-ldxr-stxr.ll48 %val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
67 %val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
77 ; CHECK: ldxr w[[LOADVAL:[0-9]+]], [x0]
83 ; GISEL: ldxr w[[LOADVAL:[0-9]+]], [x0]
86 %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
96 ; CHECK: ldxr x[[LOADVAL:[0-9]+]], [x0]
100 ; GISEL: ldxr x[[LOADVAL:[0-9]+]], [x0]
103 %val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
109 declare i64 @llvm.aarch64.ldxr.p0i8(i8*) nounwind
110 declare i64 @llvm.aarch64.ldxr.p0i16(i16*) nounwind
[all …]
Datomic-ops-not-barriers.ll19 ; CHECK: ldxr
Datomic-ops.ll88 ; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
116 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
460 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
572 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
655 ; ; CHECK: ldxr {{[xw]}}[[OLD]], [x[[ADDR]]]
779 ; OUTLINE_ATOMICS-NEXT: ldxr w8, [x9]
793 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
935 ; OUTLINE_ATOMICS-NEXT: ldxr w8, [x9]
949 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
973 ; OUTLINE_ATOMICS-NEXT: ldxr x8, [x9]
[all …]
Darm64-atomic.ll69 ; CHECK-NEXT: ldxr [[RESULT:x[0-9]+]], [x[[ADDR]]]
86 ; CHECK: ldxr w[[DEST_REG:[0-9]+]], [x0]
131 ; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
Datomic-ops-lse.ll3944 ; OUTLINE-ATOMICS-NEXT: ldxr w8, [x9]
3971 ; OUTLINE-ATOMICS-NEXT: ldxr x8, [x9]
3998 ; OUTLINE-ATOMICS-NEXT: ldxr w9, [x8]
4023 ; OUTLINE-ATOMICS-NEXT: ldxr x9, [x8]
4104 ; OUTLINE-ATOMICS-NEXT: ldxr w8, [x9]
4131 ; OUTLINE-ATOMICS-NEXT: ldxr x8, [x9]
4158 ; OUTLINE-ATOMICS-NEXT: ldxr w9, [x8]
4183 ; OUTLINE-ATOMICS-NEXT: ldxr x9, [x8]
4744 ; OUTLINE-ATOMICS-NEXT: ldxr w8, [x9]
4771 ; OUTLINE-ATOMICS-NEXT: ldxr x8, [x9]
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll42 %val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
56 %val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
65 ; CHECK: ldxr w[[LOADVAL:[0-9]+]], [x0]
70 %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
79 ; CHECK: ldxr x[[LOADVAL:[0-9]+]], [x0]
82 %val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
88 declare i64 @llvm.aarch64.ldxr.p0i8(i8*) nounwind
89 declare i64 @llvm.aarch64.ldxr.p0i16(i16*) nounwind
90 declare i64 @llvm.aarch64.ldxr.p0i32(i32*) nounwind
91 declare i64 @llvm.aarch64.ldxr.p0i64(i64*) nounwind
Datomic-ops-not-barriers.ll17 ; CHECK: ldxr
Datomic-ops.ll63 ; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
83 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
323 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
403 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
461 ; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
549 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
647 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
671 ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
863 ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
941 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
[all …]
Darm64-atomic.ll62 ; CHECK-NEXT: ldxr [[RESULT:x[0-9]+]], [x[[ADDR]]]
79 ; CHECK: ldxr w[[DEST_REG:[0-9]+]], [x0]
122 ; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dselect-ldxr-intrin.mir27 …%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 1…
49 …%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 2…
71 …%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 4…
93 …%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 8…
/external/arm-trusted-firmware/lib/locks/exclusive/aarch64/
Dspinlock.S35 ldxr w1, [x0]
/external/llvm-project/lld/test/ELF/
Daarch64-cortex-a53-843419-recognize.s501 ldxr x3, [x0]
/external/llvm/test/MC/AArch64/
Darm64-memory.s456 ldxr w6, [x1]
457 ldxr x6, [x1]
Dbasic-a64-diagnostics.s1874 ldxr sp, [sp]
Dbasic-a64-instructions.s2268 ldxr w9, [sp]
2269 ldxr x10, [x11]
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-memory.s456 ldxr w6, [x1]
457 ldxr x6, [x1]
Dbasic-a64-diagnostics.s1906 ldxr sp, [sp]
Dbasic-a64-instructions.s2251 ldxr w9, [sp]
2252 ldxr x10, [x11]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrHFP.td34 def LDXR : UnaryRR <"ldxr", 0x25, null_frag, FP64, FP128>;
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrHFP.td34 def LDXR : UnaryRR <"ldxr", 0x25, null_frag, FP64, FP128>;
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
DA55-basic-instructions.s859 ldxr w22, [sp] label
860 ldxr x11, [x29] label
861 ldxr x11, [x29] label
862 ldxr x11, [x29] label
2116 # CHECK-NEXT: 1 3 1.00 * * U ldxr w22, [sp]
2117 # CHECK-NEXT: 1 3 1.00 * * U ldxr x11, [x29]
2118 # CHECK-NEXT: 1 3 1.00 * * U ldxr x11, [x29]
2119 # CHECK-NEXT: 1 3 1.00 * * U ldxr x11, [x29]
3299 … - - - - - - - - - 1.00 - - ldxr w22, [sp]
3300 … - - - - - - - - - 1.00 - - ldxr x11, [x29]
[all …]
/external/vixl/
DREADME.md124 `stxrb`, `stxrh`, `stxr`, `ldxrb`, `ldxrh`, `ldxr`, `stxp`, `ldxp`, `stlxrb`,
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc1575 COMPARE(ldxr(w11, MemOperand(x12)), "ldxr w11, [x12]"); in TEST()
1576 COMPARE(ldxr(w13, MemOperand(sp)), "ldxr w13, [sp]"); in TEST()
1577 COMPARE(ldxr(x14, MemOperand(x15)), "ldxr x14, [x15]"); in TEST()
1578 COMPARE(ldxr(x16, MemOperand(sp)), "ldxr x16, [sp]"); in TEST()
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs882 0xe9,0x7f,0x5f,0x88 = ldxr w9, [sp]
883 0x6a,0x7d,0x5f,0xc8 = ldxr x10, [x11]

123