| /external/llvm-project/llvm/test/CodeGen/MIR/X86/ |
| D | liveout-register-mask.mir | 2 # This test ensures that the MIR parser parses the liveout register mask
38 ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, liveout($esp, $rsp, $sp, $spl),
39 …PATCHPOINT 5, 5, 0, 2, 0, $rdi, $rsi, csr_64, liveout($esp, $rsp, $sp, $spl), implicit-def dead ea…
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| /external/llvm/test/CodeGen/MIR/X86/ |
| D | liveout-register-mask.mir | 2 # This test ensures that the MIR parser parses the liveout register mask
38 ; CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl),
39 …PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, liveout(%esp, %rsp, %sp, %spl), implicit-def dead ea…
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4_live_variables.cpp | 159 ~bd->liveout[i]); in compute_live_variables()
161 bd->liveout[i] |= new_liveout; in compute_live_variables()
176 (bd->liveout[i] & in compute_live_variables()
210 if (BITSET_TEST(bd.liveout, i)) { in compute_start_end()
239 block_data[i].liveout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words); in vec4_live_variables()
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| D | brw_fs_live_variables.cpp | 171 ~bd->liveout[i]); in compute_live_variables()
173 bd->liveout[i] |= new_liveout; in compute_live_variables()
188 (bd->liveout[i] & in compute_live_variables()
240 BITSET_WORD livedefout = bd->liveout[w] & bd->defout[w]; in compute_start_end()
299 block_data[i].liveout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words); in fs_live_variables()
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| D | brw_fs_copy_propagation.cpp | 71 BITSET_WORD *liveout; member
138 bd[block->num].liveout = rzalloc_array(bd, BITSET_WORD, bitset_words); in fs_copy_prop_dataflow()
253 bd[block->num].liveout[i] = bd[block->num].copy[i]; in setup_initial_values()
257 bd[block->num].liveout[i] = ~0u; in setup_initial_values()
293 const BITSET_WORD old_liveout = bd[block->num].liveout[i]; in run()
308 bd[block->num].livein[i] &= (bd[parent->num].liveout[i] | in run()
310 livein_from_any_block |= bd[parent->num].liveout[i]; in run()
322 bd[block->num].liveout[i] = in run()
326 if (old_liveout != bd[block->num].liveout[i]) in run()
349 fprintf(stderr, "%08x", bd[block->num].liveout[i]); in dump_block_data()
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| D | brw_fs_live_variables.h | 60 BITSET_WORD *liveout; member
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| D | brw_schedule_instructions.cpp | 568 this->liveout = ralloc_array(mem_ctx, BITSET_WORD *, block_count); in instruction_scheduler()
570 this->liveout[i] = rzalloc_array(mem_ctx, BITSET_WORD, in instruction_scheduler()
586 this->liveout = NULL; in instruction_scheduler()
653 BITSET_WORD **liveout; member in instruction_scheduler
759 if (BITSET_TEST(live.block_data[block].liveout, i)) in setup_liveness()
760 BITSET_SET(liveout[block], live.vgrf_from_var[i]); in setup_liveness()
777 BITSET_SET(liveout[block], i); in setup_liveness()
842 !BITSET_TEST(liveout[block_idx], inst->src[i].nr) && in get_register_pressure_benefit()
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| D | brw_vec4_live_variables.h | 59 BITSET_WORD *liveout; member
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| D | brw_fs_dead_code_eliminate.cpp | 85 memcpy(live, live_vars.block_data[block->num].liveout, in dead_code_eliminate()
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| D | brw_vec4_dead_code_eliminate.cpp | 50 memcpy(live, live_vars.block_data[block->num].liveout, in dead_code_eliminate()
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| /external/mesa3d/src/freedreno/ir3/ |
| D | ir3_ra.c | 674 bd->liveout = rzalloc_array(bd, BITSET_WORD, bitset_words); in ra_block_compute_live_ranges()
793 (bd->use[i] | (bd->liveout[i] & ~bd->def[i])); in ra_compute_livein_liveout()
816 (succ_bd->livein[i] & ~bd->liveout[i]); in ra_compute_livein_liveout()
819 bd->liveout[i] |= new_liveout; in ra_compute_livein_liveout()
991 unsigned liveout = 0; in ra_calc_block_live_values() local
992 BITSET_FOREACH_SET (name, bd->liveout, ctx->alloc_count) { in ra_calc_block_live_values()
993 liveout += name_size(ctx, name); in ra_calc_block_live_values()
997 if (cur_live != liveout) { in ra_calc_block_live_values()
1069 print_bitset(" l/o", bd->liveout, ctx->alloc_count); in ra_add_interference()
1089 if (BITSET_TEST(bd->liveout, i)) { in ra_add_interference()
[all …]
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| D | ir3_ra.h | 132 BITSET_WORD *liveout; /* which defs reach exit point of block */ member
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| /external/tensorflow/tensorflow/compiler/mlir/xla/tests/hlo_to_lhlo_with_xla/ |
| D | passthrough.mlir | 7 // CHECK-SAME: %[[ARG1:.*]]: memref<16xi8> {lmhlo.alloc = 0 : index, lmhlo.liveout = true}
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| /external/llvm-project/llvm/test/MachineVerifier/ |
| D | live-ins-02.mir | 5 # liveins is not liveout from predecessor.
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| D | live-ins-03.mir | 5 # liveins is not liveout from predecessor.
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| D | live-ins-01.mir | 5 # liveins is not liveout from predecessor.
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| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | regbank-reassign.mir | 170 # GCN-LABEL: liveout{{$}}
173 name: liveout
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| /external/llvm/docs/ |
| D | StackMaps.rst | 382 At each callsite, a "liveout" register list is also recorded. These
388 Each entry in the liveout register list contains a DWARF register
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| /external/llvm-project/llvm/docs/ |
| D | StackMaps.rst | 386 At each callsite, a "liveout" register list is also recorded. These
392 Each entry in the liveout register list contains a DWARF register
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | README.txt | 298 Unfortunately, liveout information is currently unavailable during DAG combine
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| /external/llvm/lib/Target/ARM/ |
| D | README.txt | 298 Unfortunately, liveout information is currently unavailable during DAG combine
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| /external/llvm-project/llvm/test/Transforms/SimplifyCFG/ |
| D | fold-branch-to-common-dest.ll | 632 ; The liveout instruction can be located after the branch condition.
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | README.txt | 298 Unfortunately, liveout information is currently unavailable during DAG combine
|