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/external/llvm-project/llvm/test/MC/AArch64/
Darm64-elf-relocs.s8 add x0, x2, #:lo12:sym
9 add x0, x2, #:lo12:sym+12
10 add x0, x2, #:lo12:sym-3
38 add x0, x2, #:lo12:sym+8
101 ldrb w2, [x3, :lo12:sym]
102 ldrsb w5, [x7, #:lo12:sym]
103 ldrsb x11, [x13, :lo12:sym]
104 ldr b17, [x19, #:lo12:sym]
105 ldrb w2, [x3, :lo12:sym+15]
106 ldrsb w5, [x7, #:lo12:sym-2]
[all …]
Darm32-elf-relocs.s9 add x0, x2, #:lo12:sym
33 add x0, x2, #:lo12:sym+8
92 ldrb w2, [x3, :lo12:sym]
93 ldrsb w5, [x7, #:lo12:sym]
94 ldrsb x11, [x13, :lo12:sym]
95 ldr b17, [x19, #:lo12:sym]
131 ldrh w2, [x3, #:lo12:sym]
132 ldrsh w5, [x7, :lo12:sym]
133 ldrsh x11, [x13, #:lo12:sym]
134 ldr h17, [x19, :lo12:sym]
[all …]
Delf-reloc-ldstunsimm.s4 ldrb w0, [sp, #:lo12:some_label]
5 ldrh w0, [sp, #:lo12:some_label]
6 ldr w0, [sp, #:lo12:some_label]
7 ldr x0, [sp, #:lo12:some_label]
8 str q0, [sp, #:lo12:some_label]
/external/llvm/test/MC/AArch64/
Darm64-elf-relocs.s4 add x0, x2, #:lo12:sym
28 add x0, x2, #:lo12:sym+8
91 ldrb w2, [x3, :lo12:sym]
92 ldrsb w5, [x7, #:lo12:sym]
93 ldrsb x11, [x13, :lo12:sym]
94 ldr b17, [x19, #:lo12:sym]
130 ldrh w2, [x3, #:lo12:sym]
131 ldrsh w5, [x7, :lo12:sym]
132 ldrsh x11, [x13, #:lo12:sym]
133 ldr h17, [x19, :lo12:sym]
[all …]
Delf-reloc-ldstunsimm.s4 ldrb w0, [sp, #:lo12:some_label]
5 ldrh w0, [sp, #:lo12:some_label]
6 ldr w0, [sp, #:lo12:some_label]
7 ldr x0, [sp, #:lo12:some_label]
8 str q0, [sp, #:lo12:some_label]
/external/llvm-project/lld/test/ELF/
Daarch64-lo12-alignment.s14 ldrb w2, [x0, #:lo12:foo1] // Ok as no shift involved
15 ldrh w2, [x0, #:lo12:foo1] // Error foo1 is not 2-byte aligned
16 ldrh w2, [x0, #:lo12:foo2] // Ok as foo2 is 2-byte aligned
17 ldr w2, [x0, #:lo12:foo2] // Error foo2 is not 4-byte aligned
18 ldr w2, [x0, #:lo12:foo4] // Ok as foo4 is 4-byte aligned
19 ldr x3, [x0, #:lo12:foo4] // Error foo4 is not 8-byte aligned
20 ldr x3, [x0, #:lo12:foo8] // Ok as foo8 is 8-byte aligned
21 ldr q0, [x0, #:lo12:foo8] // Error foo8 is not 16-byte aligned
22 ldr q0, [x0, #:lo12:foo16] // Ok as foo16 is 16-byte aligned
Daarch64-relative.s9 strb w9, [x8, :lo12:.Lfoo] // R_AARCH64_LDST8_ABS_LO12_NC
10 ldr h17, [x19, :lo12:.Lfoo] // R_AARCH64_LDST16_ABS_LO12_NC
11 ldr w0, [x8, :lo12:.Lfoo] // R_AARCH64_LDST32_ABS_LO12_NC
12 ldr x0, [x8, :lo12:.Lfoo] // R_AARCH64_LDST64_ABS_LO12_NC
13 ldr q20, [x19, #:lo12:.Lfoo] // R_AARCH64_LDST128_ABS_LO12_NC
14 add x0, x0, :lo12:.Lfoo // R_AARCH64_ADD_ABS_LO12_NC
/external/llvm-project/llvm/test/CodeGen/AArch64/
Delf-globals-static.ll15 ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
16 ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
19 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
28 ; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
29 ; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
32 ; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
41 ; CHECK: ldr {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
42 ; CHECK: str {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
45 ; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var32
54 ; CHECK: ldr {{x[0-9]+}}, [x[[HIREG]], :lo12:var64]
[all …]
Dldst-unsignedimm.ll23 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
29 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
35 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
41 ; CHECK: ldrsb {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
49 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
55 ; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
61 ; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
77 ; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
83 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
89 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
[all …]
Durem-seteq-vec-nonsplat.ll9 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
11 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_1]
13 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI0_2]
19 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_3]
42 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
43 ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI1_1]
59 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]
60 ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI2_1]
77 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
79 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_1]
[all …]
Darm64-fp128.ll14 ; CHECK-NEXT: ldr q0, [x8, :lo12:lhs]
16 ; CHECK-NEXT: ldr q1, [x8, :lo12:rhs]
35 ; CHECK-NEXT: ldr q0, [x8, :lo12:lhs]
37 ; CHECK-NEXT: ldr q1, [x8, :lo12:rhs]
56 ; CHECK-NEXT: ldr q0, [x8, :lo12:lhs]
58 ; CHECK-NEXT: ldr q1, [x8, :lo12:rhs]
77 ; CHECK-NEXT: ldr q0, [x8, :lo12:lhs]
79 ; CHECK-NEXT: ldr q1, [x8, :lo12:rhs]
102 ; CHECK-NEXT: ldr q0, [x8, :lo12:lhs]
106 ; CHECK-NEXT: str w0, [x8, :lo12:var32]
[all …]
Dsrem-seteq-vec-nonsplat.ll9 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
11 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_1]
16 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI0_2]
20 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_3]
44 ; CHECK-NEXT: ldr q1, [x10, :lo12:.LCPI1_0]
65 ; CHECK-NEXT: ldr q1, [x10, :lo12:.LCPI2_0]
86 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
88 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_1]
90 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI3_2]
95 ; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI3_3]
[all …]
Datomic-ops-lse.ll25 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var8
32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
46 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
53 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
67 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
74 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
88 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var64
95 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
109 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var32
116 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
[all …]
Dmisched-fusion-addr.ll28 ; CHECK-NEXT: ldrb {{w[0-9]+}}, {{\[}}[[RB]], {{#?}}:lo12:var_8bit{{\]}}
30 ; CHECK-NEXT: strh {{w[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_16bit{{\]}}
43 ; CHECK-NEXT: ldrh {{w[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_16bit{{\]}}
45 ; CHECK-NEXT: str {{w[0-9]+}}, {{\[}}[[RW]], {{#?}}:lo12:var_32bit{{\]}}
57 ; CHECK-NEXT: ldr {{w[0-9]+}}, {{\[}}[[RW]], {{#?}}:lo12:var_32bit{{\]}}
59 ; CHECK-NEXT: str {{x[0-9]+}}, {{\[}}[[RL]], {{#?}}:lo12:var_64bit{{\]}}
71 ; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[RL]], {{#?}}:lo12:var_64bit{{\]}}
73 ; CHECK-NEXT: add {{x[0-9]+}}, [[RQ]], {{#?}}:lo12:var_128bit
84 ; CHECK-NEXT: ldr {{h[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_half{{\]}}
86 ; CHECK-NEXT: str {{s[0-9]+}}, {{\[}}[[RF]], {{#?}}:lo12:var_float{{\]}}
[all …]
Di128_volatile_load_store.ll10 ; CHECK-NEXT: add x8, x8, :lo12:x
13 ; CHECK-NEXT: add x10, x10, :lo12:y
25 ; CHECK-NEXT: add x8, x8, :lo12:x
28 ; CHECK-NEXT: add x10, x10, :lo12:y
40 ; CHECK-NEXT: add x8, x8, :lo12:x
44 ; CHECK-NEXT: add x10, x10, :lo12:y
57 ; CHECK-NEXT: add x8, x8, :lo12:x
60 ; CHECK-NEXT: add x10, x10, :lo12:y
72 ; CHECK-NEXT: add x8, x8, :lo12:x
76 ; CHECK-NEXT: add x10, x10, :lo12:y
[all …]
Datomic-ops.ll22 ; OUTLINE_ATOMICS-NEXT: add x1, x1, :lo12:var8
29 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
50 ; OUTLINE_ATOMICS-NEXT: add x1, x1, :lo12:var16
57 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
78 ; OUTLINE_ATOMICS-NEXT: add x1, x1, :lo12:var32
85 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
106 ; OUTLINE_ATOMICS-NEXT: add x1, x1, :lo12:var64
113 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
135 ; OUTLINE_ATOMICS-NEXT: add x1, x1, :lo12:var8
142 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
[all …]
Dglobal-alignment.ll13 ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
16 ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], {{#?}}:lo12:var32
31 ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:var64]
41 ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
45 ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:var32_align64]
57 ; CHECK: add x[[ADDR:[0-9]+]], x[[HIBITS]], {{#?}}:lo12:alias
73 ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], {{#?}}:lo12:yet_another_var
82 ; CHECK: add x0, [[HIBITS]], {{#?}}:lo12:test_yet_another_var
/external/llvm/test/CodeGen/AArch64/
Darm64-elf-globals.ll17 ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
18 ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
26 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8]
39 ; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
40 ; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
43 ; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
52 ; CHECK: ldr {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
53 ; CHECK: str {{w[0-9]+}}, [x[[HIREG]], :lo12:var32]
56 ; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var32
65 ; CHECK: ldr {{x[0-9]+}}, [x[[HIREG]], :lo12:var64]
[all …]
Dldst-unsignedimm.ll23 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
29 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
35 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
41 ; CHECK: ldrsb {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
49 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
55 ; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
61 ; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit]
77 ; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
83 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
89 ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit]
[all …]
Darm64-fp128.ll11 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
12 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
24 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
25 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
37 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
38 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
50 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
51 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
128 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
129 ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
[all …]
Dglobal-alignment.ll13 ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
16 ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], {{#?}}:lo12:var32
31 ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:var64]
41 ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load.
45 ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:var32_align64]
58 ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:alias]
73 ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], {{#?}}:lo12:yet_another_var
82 ; CHECK: add x0, [[HIBITS]], {{#?}}:lo12:test_yet_another_var
Darm64-aapcs.ll8 ; CHECK: str w4, [{{x[0-9]+}}, :lo12:var]
18 ; CHECK: str w3, [{{x[0-9]+}}, :lo12:var]
38 ; CHECK: str x[[EXTED]], [{{x[0-9]+}}, :lo12:var64]
43 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
48 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
53 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
56 ; CHECK: str [[LONG]], [{{x[0-9]+}}, :lo12:var64]
68 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
73 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64]
78 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64]
[all …]
/external/arm-trusted-firmware/include/arch/aarch64/
Del3_common_macros.S386 add x0, x0, :lo12:__RW_START__
388 add x1, x1, :lo12:__RW_END__
393 add x0, x0, :lo12:__NOBITS_START__
395 add x1, x1, :lo12:__NOBITS_END__
401 add x0, x0, :lo12:__BSS_START__
404 add x1, x1, :lo12:__BSS_END__
410 add x0, x0, :lo12:__COHERENT_RAM_START__
412 add x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__
419 add x0, x0, :lo12:__DATA_RAM_START__
421 add x1, x1, :lo12:__DATA_ROM_START__
[all …]
/external/boringssl/src/util/fipstools/delocate/testdata/aarch64-Basic/
Din.s18 add x1, x0, :lo12:.Llocal_data
22 add x11, x10, :lo12:.Llocal_data2+16
26 add x0, x0, :lo12:.Llocal_data
30 ldr w2, [x1, :lo12:OPENSSL_armcap_P]
34 ldr w1, [x1, :lo12:OPENSSL_armcap_P]
38 ldr q0, [x10, :lo12:.Llocal_data2]
/external/arm-trusted-firmware/plat/common/aarch64/
Dcrash_console_helpers.S76 add x0, x0, :lo12:crash_console_spinlock
81 add x1, x1, :lo12:crash_console_triggered
112 add x1, x1, :lo12:crash_console_reg_stash
119 ldr x15, [x15, :lo12:console_list] /* X15 = first console struct */
146 add x1, x1, :lo12:crash_console_reg_stash
161 add x1, x1, :lo12:crash_console_reg_stash
166 ldr x15, [x15, :lo12:console_list] /* X15 = first console struct */
183 add x1, x1, :lo12:crash_console_reg_stash

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