| /external/llvm/test/CodeGen/AArch64/ |
| D | dp2.ll | 46 ; CHECK: {{lsl|lslv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
89 ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
146 ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | dp2.ll | 46 ; CHECK: {{lsl|lslv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
89 ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
146 ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 398 lslv w1, w2, w3
399 lslv x1, x2, x3
|
| D | basic-a64-instructions.s | 1520 lslv w11, w12, w13
1521 lslv x14, x15, x16
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 398 lslv w1, w2, w3
399 lslv x1, x2, x3
|
| D | basic-a64-instructions.s | 1503 lslv w11, w12, w13
1504 lslv x14, x15, x16
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 857 COMPARE(lslv(w0, w1, w2), "lsl w0, w1, w2"); in TEST()
858 COMPARE(lslv(x3, x4, x5), "lsl x3, x4, x5"); in TEST()
|
| D | test-trace-aarch64.cc | 233 __ lslv(w9, w10, w11); in GenerateTestSequenceBase() local
234 __ lslv(x12, x13, x14); in GenerateTestSequenceBase() local
|
| D | test-cpu-features-aarch64.cc | 361 TEST_NONE(lslv_0, lslv(w0, w1, w2))
362 TEST_NONE(lslv_1, lslv(x0, x1, x2))
|
| D | test-assembler-aarch64.cc | 6145 TEST(lslv) { in TEST() argument
6163 __ lslv(x0, x0, xzr); in TEST() local
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 724 void lslv(const Register& rd, const Register& rn, const Register& rm);
|
| D | assembler-aarch64.cc | 642 void Assembler::lslv(const Register& rd, in lslv() function in vixl::aarch64::Assembler
|
| D | macro-assembler-aarch64.h | 2033 lslv(rd, rn, rm); in Lsl()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 709 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
710 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1882 void lslv(const Register& rd, const Register& rn, const Register& rm)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1299 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
1300 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1442 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
1443 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12541 "dursw\004ldxp\004ldxr\005ldxrb\005ldxrh\003lsl\004lslr\004lslv\003lsr\004"
16507 …{ 3309 /* lslv */, AArch64::LSLVWr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR32, MCK_…
16508 …{ 3309 /* lslv */, AArch64::LSLVXr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR64, MCK_…
23880 …{ 3309 /* lslv */, AArch64::LSLVWr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR32, MCK_…
23881 …{ 3309 /* lslv */, AArch64::LSLVXr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR64, MCK_…
|