| /external/llvm/test/CodeGen/AArch64/ |
| D | dp2.ll | 36 ; CHECK: {{lsr|lsrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
78 ; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
156 ; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | dp2.ll | 36 ; CHECK: {{lsr|lsrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
78 ; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
156 ; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
| /external/arm-trusted-firmware/common/aarch64/ |
| D | debug.S | 123 lsrv x0, x4, x5
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 402 lsrv w1, w2, w3
403 lsrv x1, x2, x3
|
| D | basic-a64-instructions.s | 1522 lsrv w17, w18, w19
1523 lsrv x20, x21, x22
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 402 lsrv w1, w2, w3
403 lsrv x1, x2, x3
|
| D | basic-a64-instructions.s | 1505 lsrv w17, w18, w19
1506 lsrv x20, x21, x22
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 859 COMPARE(lsrv(w6, w7, w8), "lsr w6, w7, w8"); in TEST()
860 COMPARE(lsrv(x9, x10, x11), "lsr x9, x10, x11"); in TEST()
|
| D | test-trace-aarch64.cc | 237 __ lsrv(w19, w20, w21); in GenerateTestSequenceBase() local
238 __ lsrv(x22, x23, x24); in GenerateTestSequenceBase() local
|
| D | test-cpu-features-aarch64.cc | 363 TEST_NONE(lsrv_0, lsrv(w0, w1, w2))
364 TEST_NONE(lsrv_1, lsrv(x0, x1, x2))
|
| D | test-assembler-aarch64.cc | 6201 TEST(lsrv) { in TEST() argument
6219 __ lsrv(x0, x0, xzr); in TEST() local
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 727 void lsrv(const Register& rd, const Register& rn, const Register& rm);
|
| D | assembler-aarch64.cc | 651 void Assembler::lsrv(const Register& rd, in lsrv() function in vixl::aarch64::Assembler
|
| D | macro-assembler-aarch64.h | 2048 lsrv(rd, rn, rm); in Lsr()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 711 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
712 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1896 void lsrv(const Register& rd, const Register& rn, const Register& rm)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1301 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
1302 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1444 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
1445 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12542 "lsrr\004lsrv\003mad\004madd\005match\003mla\003mls\004mneg\003mov\004mo"
16535 …{ 3323 /* lsrv */, AArch64::LSRVWr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR32, MCK_…
16536 …{ 3323 /* lsrv */, AArch64::LSRVXr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR64, MCK_…
23908 …{ 3323 /* lsrv */, AArch64::LSRVWr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR32, MCK_…
23909 …{ 3323 /* lsrv */, AArch64::LSRVXr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR64, MCK_…
|