Searched refs:max_dw (Results 1 – 16 of 16) sorted by relevance
38 if (cs->max_dw - cs->cdw < needed) in radeon_check_space()46 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_config_reg_seq()61 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_context_reg_seq()79 assert(cs->cdw + 3 <= cs->max_dw); in radeon_set_context_reg_idx()90 assert(cs->cdw + 4 <= cs->max_dw); in radeon_set_context_reg_rmw()100 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_sh_reg_seq()118 assert(cs->cdw + 3 <= cs->max_dw); in radeon_set_sh_reg_idx()133 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_uconfig_reg_seq()143 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_uconfig_reg_seq_perfctr()161 assert(cs->cdw + 3 <= cs->max_dw); in radeon_set_uconfig_reg_idx()[all …]
100 unsigned max_dw; /* Maximum number of dwords. */ member
5074 cs->max_dw = 64; in radv_pipeline_generate_pm4()5075 ctx_cs->max_dw = 256; in radv_pipeline_generate_pm4()5076 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw)); in radv_pipeline_generate_pm4()5077 ctx_cs->buf = cs->buf + cs->max_dw; in radv_pipeline_generate_pm4()5104 assert(ctx_cs->cdw <= ctx_cs->max_dw); in radv_pipeline_generate_pm4()5105 assert(cs->cdw <= cs->max_dw); in radv_pipeline_generate_pm4()5405 cs->max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 19 : 16; in radv_compute_generate_pm4()5406 cs->buf = malloc(cs->max_dw * 4); in radv_compute_generate_pm4()5411 assert(pipeline->cs.cdw <= pipeline->cs.max_dw); in radv_compute_generate_pm4()
134 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_config_reg_seq()148 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_context_reg_seq()164 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_context_reg_idx()173 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_sh_reg_seq()187 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_uconfig_reg_seq()203 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_uconfig_reg_idx()
622 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw); in r600_emit_command_buffer()995 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_ctl_const_seq()
270 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw); in r600_need_dma_space()
46 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_config_reg_seq()61 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_context_reg_seq()84 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_context_reg_idx()94 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_sh_reg_seq()109 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_uconfig_reg_seq()125 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_uconfig_reg_idx()141 assert(cs->current.cdw + 4 <= cs->current.max_dw); in radeon_set_context_reg_rmw()
265 assert((num_dw + ctx->sdma_cs->current.cdw) <= ctx->sdma_cs->current.max_dw); in si_need_dma_space()
1087 gfx_cs->current.cdw + need_gfx_dw > gfx_cs->current.max_dw) { in si_prepare_prim_discard_or_split_draw()1532 assert(cs->current.cdw <= cs->current.max_dw); in si_dispatch_prim_discard_cs_and_draw()1533 assert(gfx_cs->current.cdw <= gfx_cs->current.max_dw); in si_dispatch_prim_discard_cs_and_draw()
347 cs->base.max_dw = ib_size / 4 - 4; in radv_amdgpu_cs_create()359 cs->base.max_dw = 4096; in radv_amdgpu_cs_create()377 MIN2(cs->base.max_dw * 2, limit_dws)); in radv_amdgpu_cs_grow()397 cs->old_cs_buffers[cs->num_old_cs_buffers].max_dw = cs->base.max_dw; in radv_amdgpu_cs_grow()407 MIN2(cs->base.max_dw * 2, limit_dws)); in radv_amdgpu_cs_grow()419 cs->base.max_dw = ib_dws; in radv_amdgpu_cs_grow()427 uint64_t ib_size = MAX2(min_size * 4 + 16, cs->base.max_dw * 4 * 2); in radv_amdgpu_cs_grow()488 cs->base.max_dw = ib_size / 4 - 4; in radv_amdgpu_cs_grow()697 if (parent->base.cdw + 4 > parent->base.max_dw) in radv_amdgpu_cs_execute_secondary()705 if (parent->base.cdw + child->base.cdw > parent->base.max_dw) in radv_amdgpu_cs_execute_secondary()[all …]
72 cs->base.max_dw = 4096; in radv_null_cs_create()
200 cs->base.current.max_dw = ARRAY_SIZE(cs->csc->buf); in radeon_drm_cs_create()447 assert(rcs->current.cdw <= rcs->current.max_dw); in radeon_drm_cs_check_space()448 return rcs->current.max_dw - rcs->current.cdw >= dw; in radeon_drm_cs_check_space()601 if (rcs->current.cdw > rcs->current.max_dw) { in radeon_drm_cs_flush()641 if (cs->base.current.cdw && cs->base.current.cdw <= cs->base.current.max_dw && in radeon_drm_cs_flush()
39 - radeon: reference the correct cdw/max_dw
49 assert(size <= (cs_copy->current.max_dw - cs_copy->current.cdw)); \
812 ib->base.current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs); in amdgpu_get_new_ib()1104 assert(rcs->current.cdw <= rcs->current.max_dw); in amdgpu_cs_check_space()1118 if (rcs->current.max_dw - rcs->current.cdw >= dw) in amdgpu_cs_check_space()1149 rcs->current.max_dw += cs_epilog_dw; in amdgpu_cs_check_space()1163 assert(rcs->current.cdw <= rcs->current.max_dw); in amdgpu_cs_check_space()1172 rcs->prev[rcs->num_prev].max_dw = rcs->current.cdw; /* no modifications */ in amdgpu_cs_check_space()1179 ib->base.current.max_dw = ib->big_ib_buffer->size / 4 - cs_epilog_dw; in amdgpu_cs_check_space()1738 rcs->current.max_dw += amdgpu_cs_epilog_dws(cs); in amdgpu_cs_flush()1790 if (rcs->current.cdw > rcs->current.max_dw) { in amdgpu_cs_flush()1796 cs->main.base.current.cdw <= cs->main.base.current.max_dw && in amdgpu_cs_flush()
194 unsigned max_dw; /* Maximum number of dwords. */ member