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Searched refs:mmio_read_32 (Results 1 – 25 of 358) sorted by relevance

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/external/arm-trusted-firmware/plat/hisilicon/hikey/
Dhikey_ddr.c24 data = mmio_read_32((0xf7032000 + 0x000)); in init_pll()
28 data = mmio_read_32((0xf7032000 + 0x000)); in init_pll()
31 data = mmio_read_32((0xf7800000 + 0x000)); in init_pll()
36 data = mmio_read_32((0xf7800000 + 0x014)); in init_pll()
56 data = mmio_read_32(0xf7032000 + 0x050); in init_pll()
90 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
94 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
99 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
108 data = mmio_read_32((0xf6504000 + 0x008)); in init_freq()
115 data = mmio_read_32((0xf6504000 + 0x054)); in init_freq()
[all …]
Dhikey_bl_common.c22 data = mmio_read_32(AO_SC_TIMER_EN0); in hikey_sp804_init()
27 data = mmio_read_32(AO_SC_TIMER_EN0); in hikey_sp804_init()
30 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); in hikey_sp804_init()
33 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); in hikey_sp804_init()
36 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); in hikey_sp804_init()
39 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); in hikey_sp804_init()
44 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); in hikey_sp804_init()
98 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); in hikey_pmussi_init()
102 data = mmio_read_32(AO_SC_MCU_SUBSYS_CTRL3); in hikey_pmussi_init()
221 data = mmio_read_32(PERI_SC_CLK_SEL0); in init_mmc0_pll()
[all …]
/external/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/
Dddr_rk3368.c207 fb_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC); in ddr_get_phy_pll_freq()
208 fb_div |= (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED) & 0x1) << 8; in ddr_get_phy_pll_freq()
210 pre_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) & 0xff; in ddr_get_phy_pll_freq()
260 pctl_tim->SCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_SCFG); in ddr_reg_save()
261 pctl_tim->CMDTSTATEN = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()
263 pctl_tim->MCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG1); in ddr_reg_save()
264 pctl_tim->MCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG); in ddr_reg_save()
265 pctl_tim->PPCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_PPCFG); in ddr_reg_save()
266 pctl_tim->pctl_timing.ddrfreq = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()
268 pctl_tim->DFITCTRLDELAY = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()
[all …]
/external/arm-trusted-firmware/drivers/renesas/rcar/ddr/ddr_a/
Dddr_init_d3.c66 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_d3_1866()
86 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_d3_1866()
94 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_d3_1866()
100 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) in init_ddr_d3_1866()
128 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_d3_1866()
145 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9; in init_ddr_d3_1866()
165 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_d3_1866()
171 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_d3_1866()
176 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; in init_ddr_d3_1866()
178 r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; in init_ddr_d3_1866()
[all …]
Dddr_init_e3.c47 if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) { in init_ddr()
60 ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0); in init_ddr()
70 while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) in init_ddr()
88 r2 = mmio_read_32(0xE6790614); in init_ddr()
184 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr()
219 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr()
242 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr()
252 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) in init_ddr()
332 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr()
364 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr()
[all …]
Dddr_init_v3m.c91 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_v3m_1600()
111 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_v3m_1600()
119 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_v3m_1600()
125 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) in init_ddr_v3m_1600()
153 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_v3m_1600()
184 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_v3m_1600()
190 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_v3m_1600()
195 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 8; in init_ddr_v3m_1600()
197 r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; in init_ddr_v3m_1600()
199 r7 = mmio_read_32(DBSC_DBPDRGD_0) & 0x7; in init_ddr_v3m_1600()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/mcsi/
Dmcsi.c46 if ((mmio_read_32(cci_base_addr + FLUSH_SF) & 0x1) == 0x0) in mcsi_cache_flush()
85 support_ability = mmio_read_32(slave_base); in cci_enable_cluster_coherency()
87 pending = (mmio_read_32( in cci_enable_cluster_coherency()
90 pending = (mmio_read_32( in cci_enable_cluster_coherency()
102 while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING) in cci_enable_cluster_coherency()
118 while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING) in cci_disable_cluster_coherency()
121 config = mmio_read_32(slave_base); in cci_disable_cluster_coherency()
132 while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING) in cci_disable_cluster_coherency()
140 config = mmio_read_32(cci_base_addr + CENTRAL_CTRL_REG); in cci_secure_switch()
152 config = mmio_read_32(cci_base_addr + CENTRAL_CTRL_REG); in cci_pmu_secure_switch()
[all …]
/external/arm-trusted-firmware/drivers/rpi3/sdhost/
Drpi3_sdhost.c54 while ((mmio_read_32(reg_base + HC_COMMAND) & HC_CMD_ENABLE) in rpi3_sdhost_waitcommand()
79 status = mmio_read_32(reg_base + HC_HOSTSTATUS); in send_command_raw()
142 while (mmio_read_32(reg_base + HC_HOSTSTATUS) & HC_HSTST_HAVEDATA) { in rpi3_drain_fifo()
143 mmio_read_32(reg_base + HC_DATAPORT); in rpi3_drain_fifo()
150 edm = mmio_read_32(reg_base + HC_DEBUG); in rpi3_drain_fifo()
181 mmio_read_32(reg_base + HC_COMMAND)); in rpi3_sdhost_print_regs()
183 mmio_read_32(reg_base + HC_ARGUMENT)); in rpi3_sdhost_print_regs()
185 mmio_read_32(reg_base + HC_TIMEOUTCOUNTER)); in rpi3_sdhost_print_regs()
187 mmio_read_32(reg_base + HC_CLOCKDIVISOR)); in rpi3_sdhost_print_regs()
189 mmio_read_32(reg_base + HC_RESPONSE_0)); in rpi3_sdhost_print_regs()
[all …]
/external/arm-trusted-firmware/plat/brcm/board/stingray/src/
Dbl31_setup.c354 while (!(mmio_read_32(icfg_mem_ctrl) & in brcm_stingray_pka_meminit()
361 while (!(mmio_read_32(icfg_mem_ctrl) & in brcm_stingray_pka_meminit()
368 while (!(mmio_read_32(icfg_mem_ctrl) & in brcm_stingray_pka_meminit()
375 while (!(mmio_read_32(icfg_mem_ctrl) & in brcm_stingray_pka_meminit()
397 val = mmio_read_32(smmu_base + 0x0); in brcm_stingray_smmu_init()
406 mmio_read_32(smmu_base + 0x0), in brcm_stingray_smmu_init()
407 mmio_read_32(smmu_base + 0x4), in brcm_stingray_smmu_init()
408 mmio_read_32(smmu_base + 0x8)); in brcm_stingray_smmu_init()
411 mmio_read_32(smmu_base + 0x20), in brcm_stingray_smmu_init()
412 mmio_read_32(smmu_base + 0x24), in brcm_stingray_smmu_init()
[all …]
/external/arm-trusted-firmware/plat/intel/soc/agilex/soc/
Dagilex_memory_controller.c78 hmc_clk = mmio_read_32(AGX_SYSMGR_CORE_HMC_CLK); in check_hmc_clk()
98 data = mmio_read_32(AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT); in clear_emif()
124 data = mmio_read_32(AGX_MPFE_HMC_ADP_DDRCALSTAT); in mem_calibration()
184 data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG1); in configure_ddr_sched_ctrl_regs()
187 data = mmio_read_32(AGX_MPFE_IOHMC_DRAMADDRW); in configure_ddr_sched_ctrl_regs()
207 data = mmio_read_32(AGX_MPFE_IOHMC_DRAMTIMING0); in configure_ddr_sched_ctrl_regs()
210 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING0); in configure_ddr_sched_ctrl_regs()
215 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING1); in configure_ddr_sched_ctrl_regs()
220 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING2); in configure_ddr_sched_ctrl_regs()
223 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING3); in configure_ddr_sched_ctrl_regs()
[all …]
/external/arm-trusted-firmware/plat/mediatek/common/drivers/uart/
Duart.c70 uart->registers.lcr = mmio_read_32(UART_LCR(base)); in mt_uart_save()
73 uart->registers.efr = mmio_read_32(UART_EFR(base)); in mt_uart_save()
75 uart->registers.fcr = mmio_read_32(UART_FCR_RD(base)); in mt_uart_save()
78 uart->registers.highspeed = mmio_read_32(UART_HIGHSPEED(base)); in mt_uart_save()
79 uart->registers.fracdiv_l = mmio_read_32(UART_FRACDIV_L(base)); in mt_uart_save()
80 uart->registers.fracdiv_m = mmio_read_32(UART_FRACDIV_M(base)); in mt_uart_save()
83 uart->registers.dll = mmio_read_32(UART_DLL(base)); in mt_uart_save()
84 uart->registers.dlh = mmio_read_32(UART_DLH(base)); in mt_uart_save()
86 uart->registers.sample_count = mmio_read_32( in mt_uart_save()
88 uart->registers.sample_point = mmio_read_32( in mt_uart_save()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/spm/
Dspm.c243 isr = mmio_read_32(SPM_IRQ_MASK) & SPM_TWAM_IRQ_MASK_LSB; in spm_set_wakeup_event()
259 if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) in spm_set_pcm_wdt()
262 mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); in spm_set_pcm_wdt()
278 wakesta->assert_pc = mmio_read_32(PCM_REG_DATA_INI); in spm_get_wakeup_status()
279 wakesta->r12 = mmio_read_32(SPM_SW_RSV_0); in spm_get_wakeup_status()
280 wakesta->r12_ext = mmio_read_32(PCM_REG12_EXT_DATA); in spm_get_wakeup_status()
281 wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA); in spm_get_wakeup_status()
282 wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA); in spm_get_wakeup_status()
283 wakesta->wake_misc = mmio_read_32(SPM_BSI_D0_SR); in spm_get_wakeup_status()
284 wakesta->timer_out = mmio_read_32(SPM_BSI_D1_SR); in spm_get_wakeup_status()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/
Dspm.c104 if (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) in spm_register_init()
130 while (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) { in spm_reset_and_init_pcm()
141 con1 = mmio_read_32(SPM_PCM_CON1) & in spm_reset_and_init_pcm()
150 mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL0)); in spm_init_pcm_register()
154 mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL1)); in spm_init_pcm_register()
210 wakesta->assert_pc = mmio_read_32(SPM_PCM_REG_DATA_INI); in spm_get_wakeup_status()
211 wakesta->r12 = mmio_read_32(SPM_PCM_REG12_DATA); in spm_get_wakeup_status()
212 wakesta->raw_sta = mmio_read_32(SPM_SLEEP_ISR_RAW_STA); in spm_get_wakeup_status()
213 wakesta->wake_misc = mmio_read_32(SPM_SLEEP_WAKEUP_MISC); in spm_get_wakeup_status()
214 wakesta->timer_out = mmio_read_32(SPM_PCM_TIMER_OUT); in spm_get_wakeup_status()
[all …]
Dspm_mcdi.c238 if (((mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) & 0x1) == 1) in spm_mcdi_cpu_wake_up_event()
239 && ((mmio_read_32(SPM_CLK_CON) & CC_DISABLE_DORM_PWR) == 0)) { in spm_mcdi_cpu_wake_up_event()
242 __func__, mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT), in spm_mcdi_cpu_wake_up_event()
243 mmio_read_32(SPM_CLK_CON)); in spm_mcdi_cpu_wake_up_event()
253 while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_HANDSHAKE_ACK) in spm_mcdi_cpu_wake_up_event()
258 while (mmio_read_32(SPM_CLK_CON) != in spm_mcdi_cpu_wake_up_event()
259 (mmio_read_32(SPM_CLK_CON) | CC_DISABLE_DORM_PWR)) in spm_mcdi_cpu_wake_up_event()
264 while (mmio_read_32(SPM_CLK_CON) != in spm_mcdi_cpu_wake_up_event()
265 (mmio_read_32(SPM_CLK_CON) & ~CC_DISABLE_DORM_PWR)) in spm_mcdi_cpu_wake_up_event()
271 while (mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) != wake_up_event) in spm_mcdi_cpu_wake_up_event()
[all …]
/external/arm-trusted-firmware/plat/intel/soc/stratix10/soc/
Ds10_memory_controller.c82 hmc_clk = mmio_read_32(S10_SYSMGR_CORE_HMC_CLK); in check_hmc_clk()
102 data = mmio_read_32(S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT); in clear_emif()
128 data = mmio_read_32(S10_MPFE_HMC_ADP_DDRCALSTAT); in mem_calibration()
213 data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG1); in configure_ddr_sched_ctrl_regs()
216 data = mmio_read_32(S10_MPFE_IOHMC_DRAMADDRW); in configure_ddr_sched_ctrl_regs()
236 data = mmio_read_32(S10_MPFE_IOHMC_DRAMTIMING0); in configure_ddr_sched_ctrl_regs()
239 data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING0); in configure_ddr_sched_ctrl_regs()
244 data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING1); in configure_ddr_sched_ctrl_regs()
249 data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING2); in configure_ddr_sched_ctrl_regs()
252 data = mmio_read_32(S10_MPFE_IOHMC_CALTIMING3); in configure_ddr_sched_ctrl_regs()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8192/drivers/dcm/
Dmtk_dcm_utils.c46 ret &= ((mmio_read_32(MP_ADB_DCM_CFG0) & in dcm_mp_cpusys_top_adb_dcm_is_on()
49 ret &= ((mmio_read_32(MP_ADB_DCM_CFG4) & in dcm_mp_cpusys_top_adb_dcm_is_on()
52 ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_adb_dcm_is_on()
100 ret &= ((mmio_read_32(MP_MISC_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
103 ret &= ((mmio_read_32(MCUSYS_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
106 ret &= ((mmio_read_32(MP0_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
148 ret &= ((mmio_read_32(BUS_PLLDIV_CFG) & in dcm_mp_cpusys_top_bus_pll_div_dcm_is_on()
178 ret &= ((mmio_read_32(MP0_DCM_CFG7) & in dcm_mp_cpusys_top_core_stall_dcm_is_on()
208 ret &= ((mmio_read_32(MCSI_DCM0) & in dcm_mp_cpusys_top_cpubiu_dcm_is_on()
238 ret &= ((mmio_read_32(CPU_PLLDIV_CFG0) & in dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on()
[all …]
/external/arm-trusted-firmware/drivers/arm/gic/v2/
Dgicv2_private.h32 return mmio_read_32(base + GICD_PIDR2_GICV2); in gicd_read_pidr2()
62 return mmio_read_32(base + GICC_CTLR); in gicc_read_ctlr()
67 return mmio_read_32(base + GICC_PMR); in gicc_read_pmr()
72 return mmio_read_32(base + GICC_BPR); in gicc_read_BPR()
77 return mmio_read_32(base + GICC_IAR); in gicc_read_IAR()
82 return mmio_read_32(base + GICC_EOIR); in gicc_read_EOIR()
87 return mmio_read_32(base + GICC_HPPIR); in gicc_read_hppir()
92 return mmio_read_32(base + GICC_AHPPIR); in gicc_read_ahppir()
97 return mmio_read_32(base + GICC_DIR); in gicc_read_dir()
102 return mmio_read_32(base + GICC_IIDR); in gicc_read_iidr()
[all …]
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/
Ddram.c18 gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0); in idle_port()
23 while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & in idle_port()
33 while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & in deidle_port()
47 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); in ddr_set_pll()
49 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); in ddr_set_pll()
52 while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0) in ddr_set_pll()
67 mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); in m0_main()
68 while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0) in m0_main()
73 while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0) in m0_main()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Ddram.c19 os_reg2_val = mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)); in dram_init()
22 sdram_config.stride = (mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(4)) >> in dram_init()
40 ch->ddrconfig = mmio_read_32(MSCH_BASE(i) + MSCH_DEVICECONF); in dram_init()
42 noc->ddrtiminga0.d32 = mmio_read_32(MSCH_BASE(i) + in dram_init()
44 noc->ddrtimingb0.d32 = mmio_read_32(MSCH_BASE(i) + in dram_init()
46 noc->ddrtimingc0.d32 = mmio_read_32(MSCH_BASE(i) + in dram_init()
48 noc->devtodev0.d32 = mmio_read_32(MSCH_BASE(i) + in dram_init()
50 noc->ddrmode.d32 = mmio_read_32(MSCH_BASE(i) + MSCH_DDRMODE); in dram_init()
51 noc->agingx0 = mmio_read_32(MSCH_BASE(i) + MSCH_AGINGX0); in dram_init()
Dsuspend.c60 mmio_write_32(dst, mmio_read_32(src)); in sram_regcpy()
74 mmio_write_32(dst, mmio_read_32(src)); in dram_regcpy()
159 if ((mmio_read_32(PHY_REG(ch, 84)) >> 16) & 1) in select_per_cs_training_index()
232 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; in data_training()
238 obs_0 = mmio_read_32(PHY_REG(ch, 532)); in data_training()
239 obs_1 = mmio_read_32(PHY_REG(ch, 660)); in data_training()
240 obs_2 = mmio_read_32(PHY_REG(ch, 788)); in data_training()
273 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; in data_training()
280 obs_0 = mmio_read_32(PHY_REG(ch, 40)); in data_training()
281 obs_1 = mmio_read_32(PHY_REG(ch, 168)); in data_training()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8183/
Dplat_debug.c18 mmio_read_32(CA15M_DBG_CONTROL) & ~(BIT_CA15M_LASTPC_DIS)); in circular_buffer_setup()
26 sync_writel(VPROC_EXT_CTL, mmio_read_32(VPROC_EXT_CTL) & ~(0x1 << 1)); in circular_buffer_unlock()
29 sync_writel(CA15M_PWR_RST_CTL, mmio_read_32(CA15M_PWR_RST_CTL) & ~(0x1 << 1)); in circular_buffer_unlock()
33 (mmio_read_32(MP1_CPUTOP_PWR_CON + i * 4) & ~(0x4))|(0x4)); in circular_buffer_unlock()
48 mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 2)); in clear_all_on_mux()
50 mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 1)); in clear_all_on_mux()
57 mmio_read_32(CA15M_DBG_CONTROL) | BIT_CA15M_L2PARITY_EN); in l2c_parity_check_setup()
/external/arm-trusted-firmware/plat/mediatek/mt8192/
Dplat_mt_cirq.c78 mask->mask1 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
80 mask->mask2 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
82 mask->mask3 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
84 mask->mask4 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
86 mask->mask5 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
88 mask->mask6 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
90 mask->mask7 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
92 mask->mask8 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
94 mask->mask9 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
96 mask->mask10 = mmio_read_32((BASE_GICD_BASE + in mt_irq_mask_all()
[all …]
/external/arm-trusted-firmware/plat/marvell/armada/a8k/common/
Dplat_pm_trace.c36 mmio_read_32(AP_MSS_ATF_CORE_0_CTRL_BASE); in pm_core_0_trace()
39 mmio_read_32(AP_MSS_TIMER_BASE)); in pm_core_0_trace()
51 mmio_read_32(AP_MSS_ATF_CORE_1_CTRL_BASE); in pm_core_1_trace()
54 mmio_read_32(AP_MSS_TIMER_BASE)); in pm_core_1_trace()
66 mmio_read_32(AP_MSS_ATF_CORE_2_CTRL_BASE); in pm_core_2_trace()
69 mmio_read_32(AP_MSS_TIMER_BASE)); in pm_core_2_trace()
81 mmio_read_32(AP_MSS_ATF_CORE_3_CTRL_BASE); in pm_core_3_trace()
84 mmio_read_32(AP_MSS_TIMER_BASE)); in pm_core_3_trace()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/
Drk3399_gpio.c77 clock_state = (mmio_read_32(PMUCRU_BASE + in gpio_get_clock()
85 clock_state = (mmio_read_32(PMUCRU_BASE + in gpio_get_clock()
93 clock_state = (mmio_read_32(CRU_BASE + in gpio_get_clock()
101 clock_state = (mmio_read_32(CRU_BASE + in gpio_get_clock()
109 clock_state = (mmio_read_32(CRU_BASE + in gpio_get_clock()
172 val = mmio_read_32(PMUGRF_BASE + PMU_GRF_GPIO0A_P + in get_pull()
176 val = mmio_read_32(GRF_BASE + GRF_GPIO2A_P + in get_pull()
280 direction = !((mmio_read_32(gpio_port[port] + in get_direction()
296 value = (mmio_read_32(gpio_port[port] + EXT_PORTA) >> num) & 0x1; in get_value()
321 cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)); in plat_rockchip_save_gpio()
[all …]
/external/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/
Dpmu.c40 pd_reg = mmio_read_32(PMU_BASE + PMU_PWRDN_CON) & BIT(cpu_id); in get_cpus_pwr_domain_cfg_info()
41 apm_reg = mmio_read_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id)) & in get_cpus_pwr_domain_cfg_info()
221 val = mmio_read_32(GRF_BASE + GRF_GPIO2D_IOMUX); in rockchip_soc_system_off()
226 val = mmio_read_32(GPIO2_BASE + SWPORTA_DDR); in rockchip_soc_system_off()
231 val = mmio_read_32(GPIO2_BASE); in rockchip_soc_system_off()
255 mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); in clks_gating_suspend()
275 if (mmio_read_32(CRU_BASE + PLL_CONS(pll_id, 1)) & in pm_pll_wait_lock()
306 mmio_read_32(CRU_BASE + PLL_CONS(DPLL_ID, i)); in dpll_suspend()
327 if (mmio_read_32(CRU_BASE + PLL_CONS(DPLL_ID, 1)) & in dpll_resume()
350 mmio_read_32(CRU_BASE + PLL_CONS(pll_id, i)); in pll_suspend()
[all …]

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