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Searched refs:mmio_setbits_32 (Results 1 – 25 of 90) sorted by relevance

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/external/arm-trusted-firmware/plat/mediatek/mt8192/drivers/spmc/
Dmtspmc.c20 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_disable_gic_wakeup()
51 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
101 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(1)); in spmc_init()
[all …]
/external/arm-trusted-firmware/plat/marvell/armada/a3k/common/
Dplat_pm.c271 mmio_setbits_32(MVEBU_CPU_1_RESET_REG, BIT(MVEBU_CPU_1_RESET_BIT)); in a3700_pwr_domain_on()
304 mmio_setbits_32(MVEBU_PM_NB_CPU_PWR_CTRL_REG, MVEBU_PM_L2_FLUSH_EN); in a3700_set_gen_pwr_off_option()
330 mmio_setbits_32(MVEBU_PM_NB_PWR_DEBUG_REG, MVEBU_PM_IGNORE_CM3_SLEEP); in a3700_set_gen_pwr_off_option()
331 mmio_setbits_32(MVEBU_PM_NB_PWR_DEBUG_REG, MVEBU_PM_IGNORE_CM3_DEEP); in a3700_set_gen_pwr_off_option()
337 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_NB_SRAM_LKG_PD_EN); in a3700_set_gen_pwr_off_option()
346 mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_INTERFACE_IDLE); in a3700_set_gen_pwr_off_option()
349 mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG, MVEBU_PM_CORE_PD); in a3700_set_gen_pwr_off_option()
350 mmio_setbits_32(MVEBU_PM_CPU_1_PWR_CTRL_REG, MVEBU_PM_CORE_PD); in a3700_set_gen_pwr_off_option()
355 mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG, MVEBU_PM_CORE_SOC_PD); in a3700_set_gen_pwr_off_option()
356 mmio_setbits_32(MVEBU_PM_CPU_1_PWR_CTRL_REG, MVEBU_PM_CORE_SOC_PD); in a3700_set_gen_pwr_off_option()
[all …]
/external/arm-trusted-firmware/plat/brcm/board/stingray/src/
Dbl31_setup.c82 mmio_setbits_32(DMAC_M0_IDM_IO_CONTROL_DIRECT, BOOT_MANAGER_NS); in brcm_stingray_dma_pl330_init()
97 mmio_setbits_32(DMAC_M0_IDM_RESET_CONTROL, 0x1); in brcm_stingray_dma_pl330_init()
112 mmio_setbits_32(idm_reset_control, 0x1); in brcm_stingray_spi_pl022_init()
208 mmio_setbits_32(CDRU_MISC_CLK_ENABLE_CONTROL, in brcm_stingray_sata_init()
212 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_SATA_RESET_N); in brcm_stingray_sata_init()
220 mmio_setbits_32(SATA_APBT_IDM_PORT_REG(sata_port, in brcm_stingray_sata_init()
227 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init()
229 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init()
231 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init()
233 mmio_setbits_32(SATA_PORT_REG(sata_port, SATA_CORE_MEM_CTRL), in brcm_stingray_sata_init()
[all …]
Dihost_pm.c152 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, rst); in ihost_power_on_cluster()
178 mmio_setbits_32(CRMU_BISR_PDG_MASK, (1 << bisr)); in ihost_power_on_cluster()
233 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
252 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_MODE_CONTROL, in ihost_power_on_cluster()
256 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_CONTROL_0, in ihost_power_on_cluster()
263 mmio_setbits_32(ihost_base + A72_CRM_CLOCK_CONTROL_1, in ihost_power_on_cluster()
268 mmio_setbits_32(CDRU_CCN_REGISTER_CONTROL_1, d2xs); in ihost_power_on_cluster()
287 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
295 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_1, in ihost_power_on_cluster()
299 mmio_setbits_32(ihost_base + A72_CRM_SOFTRESETN_0, in ihost_power_on_cluster()
[all …]
Dfsx.c391 mmio_setbits_32(idm_io_control_direct, in fsx_meminit()
398 mmio_setbits_32(idm_io_control_direct, in fsx_meminit()
405 mmio_setbits_32(idm_io_control_direct, in fsx_meminit()
412 mmio_setbits_32(idm_io_control_direct, in fsx_meminit()
458 mmio_setbits_32(CDRU_GENPLL5_CONTROL1, in fs4_disable_clocks()
464 mmio_setbits_32(CDRU_GENPLL5_CONTROL1, in fs4_disable_clocks()
470 mmio_setbits_32(CDRU_GENPLL5_CONTROL1, in fs4_disable_clocks()
472 mmio_setbits_32(CDRU_GENPLL2_CONTROL1, in fs4_disable_clocks()
Dpaxb.c342 mmio_setbits_32(clk_ctrl, PAXB_RC_PCIE_RST_OUT_MASK); in paxb_perst_ctrl()
388 mmio_setbits_32(ctrl, PCIE_CORE_SOFT_RST); in pcie_core_soft_reset()
398 mmio_setbits_32(ctrl, mask); in pcie_core_pwron_switch()
478 mmio_setbits_32(CDRU_MISC_RESET_CONTROL, in pcie_ss_reset()
572 mmio_setbits_32(PCIE_CORE_USER_CFG + in paxb_cfg_dev_id()
719 mmio_setbits_32(PAXB_OFFSET(i) + in paxb_ib_regs_bypass()
744 mmio_setbits_32(PAXB_OFFSET(core_idx) + in paxb_ib_regs_init()
838 mmio_setbits_32(SR_PCIE_NIC_SECURITY_BASE + in paxb_ns_init()
842 mmio_setbits_32(SR_PCIE_NIC_SECURITY_BASE + PAXB_SECURITY_IDM_OFFSET, in paxb_ns_init()
846 mmio_setbits_32(NS3Z_PCIE_NIC_SECURITY_BASE + in paxb_ns_init()
[all …]
/external/arm-trusted-firmware/plat/imx/imx8m/
Dgpc_common.c47 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id)); in imx_set_cpu_pwr_off()
52 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
67 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_on()
69 mmio_setbits_32(IMX_GPC_BASE + CPU_PGC_UP_TRG, (1 << core_id)); in imx_set_cpu_pwr_on()
78 mmio_setbits_32(IMX_SRC_BASE + SRC_A53RCR1, (1 << core_id)); in imx_set_cpu_pwr_on()
87 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
90 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
111 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), PLAT_PDN_SLT_CTRL); in imx_a53_plat_slot_config()
112 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(3), PLAT_PUP_SLT_CTRL); in imx_a53_plat_slot_config()
115 mmio_setbits_32(IMX_GPC_BASE + PLAT_PGC_PCR, 0x1); in imx_a53_plat_slot_config()
[all …]
/external/arm-trusted-firmware/plat/imx/imx8m/imx8mq/
Dgpc.c25 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_pwr_off()
31 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_pwr_off()
41 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_AD, COREx_WFI_PDN(core_id) | in imx_set_cpu_lpm()
44 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
50 mmio_setbits_32(IMX_GPC_BASE + COREx_PGC_PCR(core_id), 0x1); in imx_set_cpu_lpm()
60 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(0), SLT_PLAT_PDN); in imx_pup_pdn_slot_config()
62 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(1), SLT_PLAT_PUP); in imx_pup_pdn_slot_config()
64 mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(2), SLT_COREx_PUP(last_core)); in imx_pup_pdn_slot_config()
88 mmio_setbits_32(IMX_GPC_BASE + LPCR_A53_BSC2, A53_LPM_STOP); in imx_set_cluster_powerdown()
101 mmio_setbits_32(IMX_GPC_BASE + A53_PLAT_PGC, 0x1); in imx_set_cluster_powerdown()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/spmc/
Dmtspmc.c52 mmio_setbits_32(reg, SW_NO_WAIT_Q); in spm_disable_cpu_auto_off()
115 mmio_setbits_32(reg, (arm64 & 1) << (i + cpu)); in mcucfg_init_archstate()
175 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
176 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
177 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
181 mmio_setbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
189 mmio_setbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
190 mmio_setbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
191 mmio_setbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
192 mmio_setbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
[all …]
/external/arm-trusted-firmware/plat/mediatek/mt8183/
Dbl31_plat_setup.c42 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->bus_pll_divider_cfg, in platform_setup_cpu()
44 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_pll_divider_cfg, in platform_setup_cpu()
46 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp2_pll_divider_cfg, in platform_setup_cpu()
57 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->cci_clk_ctrl, in platform_setup_cpu()
65 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->l2c_sram_ctrl, in platform_setup_cpu()
71 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mcu_misc_dcm_ctrl, in platform_setup_cpu()
78 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_cluster_config, in platform_setup_cpu()
81 mmio_setbits_32((uintptr_t)&mt8183_mcucfg->mp0_rgu_dcm_config, in platform_setup_cpu()
/external/arm-trusted-firmware/plat/mediatek/mt8173/
Dbl31_plat_setup.c40 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); in platform_setup_cpu()
41 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, in platform_setup_cpu()
47 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, in platform_setup_cpu()
51 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, in platform_setup_cpu()
55 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, in platform_setup_cpu()
59 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, in platform_setup_cpu()
61 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, in platform_setup_cpu()
/external/arm-trusted-firmware/drivers/brcm/
Dsotp.c80 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_read()
89 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_read()
98 mmio_setbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_read()
121 mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); in sotp_mem_read()
172 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
181 mmio_setbits_32(SOTP_PROG_CONTROL, in sotp_mem_write()
204 mmio_setbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
213 mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); in sotp_mem_write()
237 mmio_setbits_32(SOTP_CTRL_0, BIT(SOTP_CTRL_0__START)); in sotp_mem_write()
245 mmio_setbits_32(SOTP_STATUS_1, BIT(SOTP_STATUS_1__CMD_DONE)); in sotp_mem_write()
/external/arm-trusted-firmware/drivers/st/ddr/
Dstm32mp1_ddr.c398 mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); in stm32mp1_wait_sw_done_ack()
534 mmio_setbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF); in stm32mp1_ddr3_dll_off()
594 mmio_setbits_32((uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
614 mmio_setbits_32((uintptr_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE); in stm32mp1_ddr3_dll_off()
634 mmio_setbits_32((uintptr_t)&priv->phy->dllgcr, in stm32mp1_ddr3_dll_off()
638 mmio_setbits_32((uintptr_t)&priv->phy->acdllcr, DDRPHYC_ACDLLCR_DLLDIS); in stm32mp1_ddr3_dll_off()
640 mmio_setbits_32((uintptr_t)&priv->phy->dx0dllcr, in stm32mp1_ddr3_dll_off()
642 mmio_setbits_32((uintptr_t)&priv->phy->dx1dllcr, in stm32mp1_ddr3_dll_off()
644 mmio_setbits_32((uintptr_t)&priv->phy->dx2dllcr, in stm32mp1_ddr3_dll_off()
646 mmio_setbits_32((uintptr_t)&priv->phy->dx3dllcr, in stm32mp1_ddr3_dll_off()
[all …]
/external/arm-trusted-firmware/plat/allwinner/common/
Dsunxi_common.c95 mmio_setbits_32(port_base + 0x10, BIT(pin)); in sunxi_set_gpio_out()
134 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0)); in sunxi_init_platform_r_twi()
147 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); in sunxi_init_platform_r_twi()
149 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, BIT(0)); in sunxi_init_platform_r_twi()
153 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); in sunxi_init_platform_r_twi()
193 mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0)); in sunxi_execute_arisc_code()
Dsunxi_cpu_ops.c62 mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), in sunxi_cpu_off()
96 mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core)); in sunxi_cpu_on()
102 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); in sunxi_cpu_on()
104 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); in sunxi_cpu_on()
106 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); in sunxi_cpu_on()
/external/arm-trusted-firmware/plat/hisilicon/hikey960/
Dhikey960_bl1_setup.c124 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
130 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); in hikey960_ufs_reset()
132 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); in hikey960_ufs_reset()
147 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, in hikey960_ufs_reset()
149 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); in hikey960_ufs_reset()
151 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); in hikey960_ufs_reset()
156 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); in hikey960_ufs_reset()
Dhikey960_bl2_setup.c99 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
105 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); in hikey960_ufs_reset()
107 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); in hikey960_ufs_reset()
122 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, in hikey960_ufs_reset()
124 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); in hikey960_ufs_reset()
126 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); in hikey960_ufs_reset()
131 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); in hikey960_ufs_reset()
/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/
Dmtcmos.c136 mmio_setbits_32(reg_pwr_con, PWR_ISO); in mtcmos_ctrl_little_off()
137 mmio_setbits_32(reg_pwr_con, SRAM_CKISO); in mtcmos_ctrl_little_off()
139 mmio_setbits_32(reg_l1_pdn, L1_PDN); in mtcmos_ctrl_little_off()
145 mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS); in mtcmos_ctrl_little_off()
204 mmio_setbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN); in mtcmos_non_cpu_ctrl()
264 mmio_setbits_32(SPM_PCM_RESERVE2, power_ctrl); in mtcmos_non_cpu_ctrl()
/external/arm-trusted-firmware/drivers/st/gpio/
Dstm32_gpio.c215 mmio_setbits_32(base + GPIO_MODE_OFFSET, in set_gpio()
219 mmio_setbits_32(base + GPIO_TYPE_OFFSET, BIT(pin)); in set_gpio()
226 mmio_setbits_32(base + GPIO_SPEED_OFFSET, speed << (pin << 1)); in set_gpio()
230 mmio_setbits_32(base + GPIO_PUPD_OFFSET, pull << (pin << 1)); in set_gpio()
235 mmio_setbits_32(base + GPIO_AFRL_OFFSET, in set_gpio()
241 mmio_setbits_32(base + GPIO_AFRH_OFFSET, in set_gpio()
279 mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin)); in set_gpio_secure_cfg()
/external/arm-trusted-firmware/plat/intel/soc/common/soc/
Dsocfpga_reset_manager.c87 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask); in config_hps_hs_before_warm_reset()
105 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0); in socfpga_bridges_enable()
121 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1); in socfpga_bridges_disable()
135 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), in socfpga_bridges_disable()
138 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), in socfpga_bridges_disable()
/external/arm-trusted-firmware/plat/mediatek/mt8183/drivers/gpio/
Dmtgpio.c241 mmio_setbits_32(pupd_addr, 1U << pupd_offset); in mt_set_gpio_pull_enable_chip()
245 mmio_setbits_32(pullen_addr, in mt_set_gpio_pull_enable_chip()
250 mmio_setbits_32(pupd_addr, 1U << pupd_offset); in mt_set_gpio_pull_enable_chip()
256 mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 1)); in mt_set_gpio_pull_enable_chip()
259 mmio_setbits_32(pupd_addr, 3U << pupd_offset); in mt_set_gpio_pull_enable_chip()
302 mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 2)); in mt_set_gpio_pull_select_chip()
311 mmio_setbits_32(pullsel_addr, in mt_set_gpio_pull_select_chip()
316 mmio_setbits_32(pupd_addr, 1U << (pupd_offset + 2)); in mt_set_gpio_pull_select_chip()
/external/arm-trusted-firmware/plat/intel/soc/common/
Dsocfpga_psci.c50 mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id); in socfpga_pwr_domain_on()
81 mmio_setbits_32(SOCFPGA_RSTMGR(MPUMODRST), 1 << cpu_id); in socfpga_pwr_domain_suspend()
164 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_SET); in socfpga_system_reset2()
167 mmio_setbits_32(SOCFPGA_RSTMGR(COLDMODRST), 0x100); in socfpga_system_reset2()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/
Ddram.c21 mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in idle_port()
60 mmio_setbits_32(PHY_REG(0, 927), (1 << 22)); in m0_main()
61 mmio_setbits_32(PHY_REG(1, 927), (1 << 22)); in m0_main()
/external/arm-trusted-firmware/plat/arm/board/n1sdp/
Dn1sdp_bl31_setup.c117 mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN); in dmc_ecc_setup()
118 mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN); in dmc_ecc_setup()
147 mmio_setbits_32(N1SDP_REMOTE_DMC0_ERR0CTLR0_REG, in remote_dmc_ecc_setup()
149 mmio_setbits_32(N1SDP_REMOTE_DMC1_ERR0CTLR0_REG, in remote_dmc_ecc_setup()
/external/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/
Dspm_suspend.c284 mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON); in bigcore_pll_on()
286 mmio_setbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN); in bigcore_pll_on()
292 mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN); in bigcore_pll_off()

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