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Searched refs:neg_hi (Results 1 – 25 of 38) sorted by relevance

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/external/llvm-project/llvm/test/MC/AMDGPU/
Ddl-insts.s770 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[0,0,0]
772 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[1,0,0]
774 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[0,1,0]
776 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[0,0,1]
778 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[1,1,0]
780 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[1,0,1]
782 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[1,1,1]
784 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,0,0] neg_hi:[0,0,0]
786 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,0,0] neg_hi:[0,0,0]
788 v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,1,0] neg_hi:[0,0,0]
[all …]
Dvop3p.s61 v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[0,0,0] neg_hi:[0,0,0]
64 v_pk_fma_f16 v8, v0, s0, v1 op_sel:[0,0,0] op_sel_hi:[1,1,1] neg_lo:[0,0,0] neg_hi:[0,0,0]
83 v_pk_fma_f16 v8, v0, s0, v1 neg_hi:[1,1,1]
86 v_pk_fma_f16 v8, v0, s0, v1 neg_lo:[1,1,1] neg_hi:[1,1,1]
98 v_pk_fma_f16 v8, v0, s0, v1 neg_hi:[1,0,0]
101 v_pk_fma_f16 v8, v0, s0, v1 neg_hi:[0,1,0]
104 v_pk_fma_f16 v8, v0, s0, v1 neg_hi:[0,0,1]
Ddl-insts-err.s118 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi
120 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:
122 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[
124 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:]
126 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[]
128 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[,]
130 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[,0]
132 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[0,2]
134 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[2,0]
136 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[2,2]
[all …]
Dgfx908_err_pos.s14 v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[0,2]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dfmul.v2f16.ll29 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 neg_lo:[1,0] neg_hi:[1,0]
51 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
73 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1 neg_lo:[1,1] neg_hi:[1,1]
148 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v2 neg_lo:[1,0] neg_hi:[1,0]
149 ; GFX9-NEXT: v_pk_mul_f16 v1, v1, v3 neg_lo:[1,0] neg_hi:[1,0]
177 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1]
178 ; GFX9-NEXT: v_pk_mul_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1]
206 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v2 neg_lo:[1,1] neg_hi:[1,1]
207 ; GFX9-NEXT: v_pk_mul_f16 v1, v1, v3 neg_lo:[1,1] neg_hi:[1,1]
269 ; GFX9-NEXT: v_pk_mul_f16 v0, v0, v3 neg_lo:[1,0] neg_hi:[1,0]
[all …]
Dllvm.amdgcn.fdot2.ll44 ; GFX906-NEXT: v_dot2_f32_f16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
51 ; GFX10-NEXT: v_dot2_f32_f16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
62 ; GFX906-NEXT: v_dot2_f32_f16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
69 ; GFX10-NEXT: v_dot2_f32_f16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
80 ; GFX906-NEXT: v_dot2_f32_f16 v0, v1, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0]
87 ; GFX10-NEXT: v_dot2_f32_f16 v0, v1, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0]
Dmul.v2i16.ll27 ; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v1 neg_lo:[1,0] neg_hi:[1,0]
48 ; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
69 ; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v1 neg_lo:[1,1] neg_hi:[1,1]
Dllvm.amdgcn.sdot2.ll197 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
203 ; GFX908-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
210 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
222 ; GFX906-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
228 ; GFX908-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
235 ; GFX10-NEXT: v_dot2_i32_i16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
Dllvm.amdgcn.udot2.ll197 ; GFX906-NEXT: v_dot2_u32_u16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
203 ; GFX908-NEXT: v_dot2_u32_u16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
210 ; GFX10-NEXT: v_dot2_u32_u16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
222 ; GFX906-NEXT: v_dot2_u32_u16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
228 ; GFX908-NEXT: v_dot2_u32_u16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
235 ; GFX10-NEXT: v_dot2_u32_u16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
Dadd.v2i16.ll27 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[1,0] neg_hi:[1,0]
48 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]
69 ; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 neg_lo:[1,1] neg_hi:[1,1]
Dfma.ll155 ; GFX9-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
200 ; GFX9-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
254 ; GFX9-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Ddl-insts.txt1111 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[1,0,0] ; encoding: [0x00,0x41,0xa3,0xd3,0x01,0x05,0x…
1114 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[0,1,0] ; encoding: [0x00,0x42,0xa3,0xd3,0x01,0x05,0x…
1117 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[0,0,1] ; encoding: [0x00,0x44,0xa3,0xd3,0x01,0x05,0x…
1120 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[1,1,0] ; encoding: [0x00,0x43,0xa3,0xd3,0x01,0x05,0x…
1123 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[1,0,1] ; encoding: [0x00,0x45,0xa3,0xd3,0x01,0x05,0x…
1126 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[1,1,1] ; encoding: [0x00,0x47,0xa3,0xd3,0x01,0x05,0x…
1150 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_hi:[1,0,0] ; encoding: [0x00,0x41,0xa3,0xd3,0x01,0x05,0x…
1153 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[1,0,0] neg_hi:[1,0,0] ; encoding: [0x00,0x41,0xa3,0x…
1156 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,1,0] neg_hi:[1,0,0] ; encoding: [0x00,0x41,0xa3,0x…
1159 # CHECK: v_dot2_f32_f16 v0, v1, v2, v3 neg_lo:[0,0,1] neg_hi:[1,0,0] ; encoding: [0x00,0x41,0xa3,0x…
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dpacked-op-sel.ll41 …6 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[SCALAR0]] op_sel_hi:[1,1,0] neg_lo:[0,0,1] neg_hi:[0,0,1]{{$}}
70 …6 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[SCALAR0]] op_sel_hi:[1,1,0] neg_lo:[0,0,1] neg_hi:[0,0,1]{{$}}
157 ; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[SCALAR0]] op_sel_hi:[1,1,0] neg_hi:[0,0,1]{{…
184 ; GCN: v_pk_add_u16 v{{[0-9]+}}, [[VEC0]], [[SCALAR0]] op_sel_hi:[1,0] neg_lo:[0,1] neg_hi:[0,1]{{$…
239 ; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[PACKED]] neg_lo:[0,0,1] neg_hi:[0,0,1]{{$}}
270 ; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[VEC2]] op_sel:[0,0,1] neg_lo:[0,0,1] neg_hi:…
298 ; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[VEC2]] neg_hi:[0,0,1]{{$}}
437 …}, [[VEC0]], [[VEC1]], [[VEC2]] op_sel:[0,0,1] op_sel_hi:[1,1,0] neg_lo:[0,0,1] neg_hi:[0,0,1]{{$}}
522 ; GCN: v_pk_fma_f16 v{{[0-9]+}}, [[VEC0]], [[VEC1]], [[VEC2]] neg_hi:[0,0,1]{{$}}
Dfsub.f16.ll92 ; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]] neg_lo:[0,1] neg_hi:[0,1]
128 ; GFX9: v_pk_add_f16 v[[R_V2_F16:[0-9]+]], v[[B_V2_F16]], [[K]] neg_lo:[1,0] neg_hi:[1,0]
Dfneg.f16.ll120 ; GFX9: v_pk_mul_f16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} neg_lo:[1,0] neg_hi:[1,0]{{$}}
Dstrict_fma.f16.ll143 ; GFX9-NEXT: v_pk_fma_f16 v0, v0, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0]
/external/llvm-project/llvm/docs/AMDGPU/
DAMDGPUAsmGFX1011.rst73 …dgpu_synid1011_type_dev>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_h…
DAMDGPUAsmGFX906.rst66 …mdgpu_synid906_type_dev>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_h…
/external/llvm-project/llvm/lib/Target/AMDGPU/
DVOPInstructions.td302 // neg, neg_hi, op_sel put in srcN_modifiers
312 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0
313 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1
314 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2
DSIInstrInfo.td1142 def neg_hi : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>;
1682 neg_lo:$neg_lo, neg_hi:$neg_hi),
1686 neg_lo:$neg_lo, neg_hi:$neg_hi)),
1694 neg_lo:$neg_lo, neg_hi:$neg_hi),
1699 neg_lo:$neg_lo, neg_hi:$neg_hi))
1913 string mods = !if(HasModifiers, "$neg_lo$neg_hi", "");
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOPInstructions.td296 // neg, neg_hi, op_sel put in srcN_modifiers
306 let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); // neg_hi src0
307 let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); // neg_hi src1
308 let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0); // neg_hi src2
DSIInstrInfo.td1096 def neg_hi : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>;
1690 neg_lo:$neg_lo, neg_hi:$neg_hi),
1694 neg_lo:$neg_lo, neg_hi:$neg_hi)),
1702 neg_lo:$neg_lo, neg_hi:$neg_hi),
1707 neg_lo:$neg_lo, neg_hi:$neg_hi))
1921 string mods = !if(HasModifiers, "$neg_lo$neg_hi", "");
/external/llvm-project/llvm/docs/
DAMDGPUModifierSyntax.rst1644 neg_hi subsection
1664 neg_hi:[{0..1}] Select affected operands for instructions with 1 source operand.
1665 … neg_hi:[{0..1},{0..1}] Select affected operands for instructions with 2 source operands.
1666 … neg_hi:[{0..1},{0..1},{0..1}] Select affected operands for instructions with 3 source operands.
1677 neg_hi:[1,0]
1678 neg_hi:[0,1,1]
/external/mesa3d/src/compiler/glsl/
Dlower_instructions.cpp1674 ir_variable *neg_hi = in imul_high_to_mul() local
1678 i.insert_before(neg_hi); in imul_high_to_mul()
1679 i.insert_before(assign(neg_hi, add(bit_not(u2i(hi)), in imul_high_to_mul()
1685 ir->operands[1] = new(ir) ir_dereference_variable(neg_hi); in imul_high_to_mul()
/external/mesa3d/src/amd/compiler/
Daco_print_ir.cpp755 if (vop3->neg_lo[i] && vop3->neg_hi[i]) in aco_print_instr()
759 else if (vop3->neg_hi[i]) in aco_print_instr()

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