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/external/llvm-project/llvm/test/CodeGen/NVPTX/
Dintrinsic-old.ll41 ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.x;
42 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !range ![[BLK_SIZE_XY:[0-9]+]]
44 %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
49 ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.y;
50 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.y(), !range ![[BLK_SIZE_XY]]
52 %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
57 ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.z;
58 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.z(), !range ![[BLK_SIZE_Z:[0-9]+]]
60 %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.z()
65 ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.w;
[all …]
Dbug22322.ll14 %1 = tail call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
43 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x() #1
/external/llvm/test/CodeGen/NVPTX/
Dintrinsic-old.ll41 ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.x;
42 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !range ![[BLK_SIZE_XY:[0-9]+]]
44 %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
49 ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.y;
50 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.y(), !range ![[BLK_SIZE_XY]]
52 %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
57 ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.z;
58 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.z(), !range ![[BLK_SIZE_Z:[0-9]+]]
60 %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.z()
65 ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.w;
[all …]
Dbug22322.ll14 %1 = tail call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
43 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x() #1
/external/llvm-project/mlir/test/Dialect/LLVMIR/
Dnvvm.mlir10 // CHECK: nvvm.read.ptx.sreg.ntid.x : !llvm.i32
11 %3 = nvvm.read.ptx.sreg.ntid.x : !llvm.i32
12 // CHECK: nvvm.read.ptx.sreg.ntid.y : !llvm.i32
13 %4 = nvvm.read.ptx.sreg.ntid.y : !llvm.i32
14 // CHECK: nvvm.read.ptx.sreg.ntid.z : !llvm.i32
15 %5 = nvvm.read.ptx.sreg.ntid.z : !llvm.i32
/external/llvm-project/mlir/test/Target/
Dnvvmir.mlir10 // CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
11 %4 = nvvm.read.ptx.sreg.ntid.x : !llvm.i32
12 // CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
13 %5 = nvvm.read.ptx.sreg.ntid.y : !llvm.i32
14 // CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ntid.z()
15 %6 = nvvm.read.ptx.sreg.ntid.z : !llvm.i32
/external/llvm-project/mlir/include/mlir/Dialect/LLVMIR/
DNVVMOps.td69 def NVVM_BlockDimXOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ntid.x">;
70 def NVVM_BlockDimYOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ntid.y">;
71 def NVVM_BlockDimZOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ntid.z">;
/external/llvm-project/llvm/test/Transforms/OpenMP/
Dglobalization_remarks.ll21 %nvptx_num_threads = tail call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !dbg !12, !range !13
40 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x() #1
/external/llvm-project/mlir/test/Conversion/GPUToNVVM/
Dgpu-to-nvvm.mlir22 // CHECK: = nvvm.read.ptx.sreg.ntid.x : !llvm.i32
25 // CHECK: = nvvm.read.ptx.sreg.ntid.y : !llvm.i32
28 // CHECK: = nvvm.read.ptx.sreg.ntid.z : !llvm.i32
/external/strace/
Dstrace.c1063 unsigned int ntid = 0, nerr = 0; in attach_tcb() local
1078 ++ntid; in attach_tcb()
1095 if (ntid > nerr) in attach_tcb()
1098 tcp->pid, ntid - nerr + 1); in attach_tcb()
/external/llvm-project/llvm/docs/
DNVPTXUsage.rst207 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
208 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
209 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.z()
230 ``blockDim`` ``@llvm.nvvm.read.ptx.sreg.ntid.*``
559 ``i32 @llvm.nvvm.read.ptx.sreg.ntid.{x,y,z}`` blockDim.{x,y,z}
/external/llvm/docs/
DNVPTXUsage.rst207 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
208 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
209 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.z()
230 ``blockDim`` ``@llvm.nvvm.read.ptx.sreg.ntid.*``
567 ``i32 @llvm.nvvm.read.ptx.sreg.ntid.{x,y,z}`` blockDim.{x,y,z}
/external/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td6999 PTX_READ_SREG_R32<"ntid.x", int_nvvm_read_ptx_sreg_ntid_x>;
7001 PTX_READ_SREG_R32<"ntid.y", int_nvvm_read_ptx_sreg_ntid_y>;
7003 PTX_READ_SREG_R32<"ntid.z", int_nvvm_read_ptx_sreg_ntid_z>;
7005 PTX_READ_SREG_R32<"ntid.w", int_nvvm_read_ptx_sreg_ntid_w>;
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td7279 PTX_READ_SREG_R32<"ntid.x", int_nvvm_read_ptx_sreg_ntid_x>;
7281 PTX_READ_SREG_R32<"ntid.y", int_nvvm_read_ptx_sreg_ntid_y>;
7283 PTX_READ_SREG_R32<"ntid.z", int_nvvm_read_ptx_sreg_ntid_z>;
7285 PTX_READ_SREG_R32<"ntid.w", int_nvvm_read_ptx_sreg_ntid_w>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td7279 PTX_READ_SREG_R32<"ntid.x", int_nvvm_read_ptx_sreg_ntid_x>;
7281 PTX_READ_SREG_R32<"ntid.y", int_nvvm_read_ptx_sreg_ntid_y>;
7283 PTX_READ_SREG_R32<"ntid.z", int_nvvm_read_ptx_sreg_ntid_z>;
7285 PTX_READ_SREG_R32<"ntid.w", int_nvvm_read_ptx_sreg_ntid_w>;
/external/llvm-project/llvm/test/DebugInfo/NVPTX/
Ddebug-info.ll30 ; CHECK: mov.u32 %r{{.+}}, %ntid.x;
68 %1 = tail call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() #3, !dbg !617, !range !661
8413 declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x() #1
/external/llvm/include/llvm/IR/
DIntrinsicsNVVM.td3657 defm int_nvvm_read_ptx_sreg_ntid : PTXReadSRegIntrinsic_v4i32<"ntid">;
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsNVVM.td3970 defm int_nvvm_read_ptx_sreg_ntid : PTXReadSRegIntrinsic_v4i32<"ntid">;
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsicsNVVM.td3963 defm int_nvvm_read_ptx_sreg_ntid : PTXReadSRegIntrinsic_v4i32<"ntid">;
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen3156 nvvm_read_ptx_sreg_ntid_w, // llvm.nvvm.read.ptx.sreg.ntid.w
3157 nvvm_read_ptx_sreg_ntid_x, // llvm.nvvm.read.ptx.sreg.ntid.x
3158 nvvm_read_ptx_sreg_ntid_y, // llvm.nvvm.read.ptx.sreg.ntid.y
3159 nvvm_read_ptx_sreg_ntid_z, // llvm.nvvm.read.ptx.sreg.ntid.z
9180 "llvm.nvvm.read.ptx.sreg.ntid.w",
9181 "llvm.nvvm.read.ptx.sreg.ntid.x",
9182 "llvm.nvvm.read.ptx.sreg.ntid.y",
9183 "llvm.nvvm.read.ptx.sreg.ntid.z",
17065 1, // llvm.nvvm.read.ptx.sreg.ntid.w
17066 1, // llvm.nvvm.read.ptx.sreg.ntid.x
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen3162 nvvm_read_ptx_sreg_ntid_w, // llvm.nvvm.read.ptx.sreg.ntid.w
3163 nvvm_read_ptx_sreg_ntid_x, // llvm.nvvm.read.ptx.sreg.ntid.x
3164 nvvm_read_ptx_sreg_ntid_y, // llvm.nvvm.read.ptx.sreg.ntid.y
3165 nvvm_read_ptx_sreg_ntid_z, // llvm.nvvm.read.ptx.sreg.ntid.z
9220 "llvm.nvvm.read.ptx.sreg.ntid.w",
9221 "llvm.nvvm.read.ptx.sreg.ntid.x",
9222 "llvm.nvvm.read.ptx.sreg.ntid.y",
9223 "llvm.nvvm.read.ptx.sreg.ntid.z",
17160 1, // llvm.nvvm.read.ptx.sreg.ntid.w
17161 1, // llvm.nvvm.read.ptx.sreg.ntid.x
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen3162 nvvm_read_ptx_sreg_ntid_w, // llvm.nvvm.read.ptx.sreg.ntid.w
3163 nvvm_read_ptx_sreg_ntid_x, // llvm.nvvm.read.ptx.sreg.ntid.x
3164 nvvm_read_ptx_sreg_ntid_y, // llvm.nvvm.read.ptx.sreg.ntid.y
3165 nvvm_read_ptx_sreg_ntid_z, // llvm.nvvm.read.ptx.sreg.ntid.z
9220 "llvm.nvvm.read.ptx.sreg.ntid.w",
9221 "llvm.nvvm.read.ptx.sreg.ntid.x",
9222 "llvm.nvvm.read.ptx.sreg.ntid.y",
9223 "llvm.nvvm.read.ptx.sreg.ntid.z",
17160 1, // llvm.nvvm.read.ptx.sreg.ntid.w
17161 1, // llvm.nvvm.read.ptx.sreg.ntid.x
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen3162 nvvm_read_ptx_sreg_ntid_w, // llvm.nvvm.read.ptx.sreg.ntid.w
3163 nvvm_read_ptx_sreg_ntid_x, // llvm.nvvm.read.ptx.sreg.ntid.x
3164 nvvm_read_ptx_sreg_ntid_y, // llvm.nvvm.read.ptx.sreg.ntid.y
3165 nvvm_read_ptx_sreg_ntid_z, // llvm.nvvm.read.ptx.sreg.ntid.z
9220 "llvm.nvvm.read.ptx.sreg.ntid.w",
9221 "llvm.nvvm.read.ptx.sreg.ntid.x",
9222 "llvm.nvvm.read.ptx.sreg.ntid.y",
9223 "llvm.nvvm.read.ptx.sreg.ntid.z",
17160 1, // llvm.nvvm.read.ptx.sreg.ntid.w
17161 1, // llvm.nvvm.read.ptx.sreg.ntid.x
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen3162 nvvm_read_ptx_sreg_ntid_w, // llvm.nvvm.read.ptx.sreg.ntid.w
3163 nvvm_read_ptx_sreg_ntid_x, // llvm.nvvm.read.ptx.sreg.ntid.x
3164 nvvm_read_ptx_sreg_ntid_y, // llvm.nvvm.read.ptx.sreg.ntid.y
3165 nvvm_read_ptx_sreg_ntid_z, // llvm.nvvm.read.ptx.sreg.ntid.z
9220 "llvm.nvvm.read.ptx.sreg.ntid.w",
9221 "llvm.nvvm.read.ptx.sreg.ntid.x",
9222 "llvm.nvvm.read.ptx.sreg.ntid.y",
9223 "llvm.nvvm.read.ptx.sreg.ntid.z",
17160 1, // llvm.nvvm.read.ptx.sreg.ntid.w
17161 1, // llvm.nvvm.read.ptx.sreg.ntid.x
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc4647 "llvm.nvvm.read.ptx.sreg.ntid.w",
4648 "llvm.nvvm.read.ptx.sreg.ntid.x",
4649 "llvm.nvvm.read.ptx.sreg.ntid.y",
4650 "llvm.nvvm.read.ptx.sreg.ntid.z",
14780 1, // llvm.nvvm.read.ptx.sreg.ntid.w
14781 1, // llvm.nvvm.read.ptx.sreg.ntid.x
14782 1, // llvm.nvvm.read.ptx.sreg.ntid.y
14783 1, // llvm.nvvm.read.ptx.sreg.ntid.z

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