| /external/mesa3d/src/amd/vulkan/ |
| D | radv_shader.h | 90 uint8_t num_patches; member
339 uint32_t num_patches; member
562 unsigned num_patches = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices) * 4; in get_tcs_num_patches() local
577 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size)); in get_tcs_num_patches()
580 num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size); in get_tcs_num_patches()
584 num_patches = MIN2(num_patches, 40); in get_tcs_num_patches()
589 num_patches = MIN2(num_patches, one_wave); in get_tcs_num_patches()
591 return num_patches; in get_tcs_num_patches()
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| D | radv_pipeline.c | 1392 …ia_multi_vgt_param.primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; in radv_compute_ia_multi_vgt_param_helpers()
2802 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = in radv_fill_shader_info()
2803 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches; in radv_fill_shader_info()
2832 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = in radv_fill_shader_info()
2833 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches; in radv_fill_shader_info()
3372 …keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.n… in radv_create_shaders()
3397 …keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.n… in radv_create_shaders()
4511 unsigned num_tcs_input_cp, num_tcs_output_cp, num_patches; in radv_pipeline_generate_tess_state() local
4516 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; in radv_pipeline_generate_tess_state()
4518 ls_hs_config = S_028B58_NUM_PATCHES(num_patches) | in radv_pipeline_generate_tess_state()
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| D | radv_nir_to_llvm.c | 177 unsigned num_patches = ctx->tcs_num_patches; in get_tcs_out_patch0_offset() local
179 output_patch0_offset *= num_patches; in get_tcs_out_patch0_offset()
195 unsigned num_patches = ctx->tcs_num_patches; in get_tcs_out_patch0_patch_data_offset() local
197 output_patch0_offset *= num_patches; in get_tcs_out_patch0_patch_data_offset()
404 uint32_t num_patches = ctx->tcs_num_patches; in get_non_vertex_index_offset() local
414 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false); in get_non_vertex_index_offset()
3956 ctx.tcs_num_patches = args->options->key.tes.num_patches; in ac_translate_nir_to_llvm()
4054 args->shader_info->tcs.num_patches = ctx.tcs_num_patches; in ac_translate_nir_to_llvm()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_state_draw.c | 69 unsigned *num_patches) in si_emit_derived_tess_state() argument
106 *num_patches = sctx->last_num_patches; in si_emit_derived_tess_state()
144 *num_patches = 256 / max_verts_per_patch; in si_emit_derived_tess_state()
154 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size + output_patch_size)); in si_emit_derived_tess_state()
157 *num_patches = in si_emit_derived_tess_state()
158 MIN2(*num_patches, (sctx->screen->tess_offchip_block_dw_size * 4) / output_patch_size); in si_emit_derived_tess_state()
164 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */ in si_emit_derived_tess_state()
170 *num_patches = MIN2(*num_patches, 16); /* recommended */ in si_emit_derived_tess_state()
176 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch; in si_emit_derived_tess_state()
180 *num_patches = (temp_verts_per_tg & ~(wave_size - 1)) / max_verts_per_patch; in si_emit_derived_tess_state()
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| D | si_shader_llvm_tess.c | 218 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices; in get_tcs_tes_buffer_address() local
222 num_patches = si_unpack_param(ctx, ctx->tcs_offchip_layout, 0, 6); in get_tcs_tes_buffer_address()
223 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch, num_patches, ""); in get_tcs_tes_buffer_address()
231 param_stride = num_patches; in get_tcs_tes_buffer_address()
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| /external/libxaac/decoder/ |
| D | ixheaacd_lpp_tran.c | 577 WORD num_patches = hf_generator->pstr_settings->num_patches; in ixheaacd_filter1_lp() local
582 memset(bw_index, 0, sizeof(WORD32) * num_patches); in ixheaacd_filter1_lp()
679 while (patch < num_patches) { in ixheaacd_filter1_lp()
757 WORD32 num_patches = hf_generator->pstr_settings->num_patches; in ixheaacd_low_pow_hf_generator() local
765 ixheaacd_add16(patch_param[num_patches - 1].dst_start_band, in ixheaacd_low_pow_hf_generator()
766 patch_param[num_patches - 1].num_bands_in_patch); in ixheaacd_low_pow_hf_generator()
821 while (patch < num_patches) { in ixheaacd_low_pow_hf_generator()
876 WORD32 num_patches = hf_generator->pstr_settings->num_patches; in ixheaacd_hf_generator() local
886 ixheaacd_add16(patch_param[num_patches - 1].dst_start_band, in ixheaacd_hf_generator()
887 patch_param[num_patches - 1].num_bands_in_patch); in ixheaacd_hf_generator()
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| D | ixheaacd_lpp_tran.h | 51 WORD16 num_patches; member
86 WORD32 num_patches; member
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| D | ixheaacd_esbr_envcal.c | 819 WORD32 num_patches; in ixheaacd_createlimiterbands() local
828 num_patches = 0; in ixheaacd_createlimiterbands()
831 if (x_over_qmf[i] != 0) num_patches++; in ixheaacd_createlimiterbands()
834 if (x_over_qmf[i] != 0) num_patches++; in ixheaacd_createlimiterbands()
836 for (i = 0; i < num_patches; i++) { in ixheaacd_createlimiterbands()
840 num_patches = patch_param->num_patches; in ixheaacd_createlimiterbands()
841 for (i = 0; i < num_patches; i++) { in ixheaacd_createlimiterbands()
856 for (k = 1; k < num_patches; k++) { in ixheaacd_createlimiterbands()
860 gate_mode[i] = ixheaacd_num_bands + num_patches - 1; in ixheaacd_createlimiterbands()
879 for (k = 0; k <= num_patches; k++) { in ixheaacd_createlimiterbands()
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| D | ixheaacd_sbrdec_lpfuncs.c | 95 const ia_patch_param_struct *p_str_patch_param, WORD16 num_patches, in ixheaacd_derive_lim_band_tbl() argument
122 for (k = 0; k < num_patches; k++) { in ixheaacd_derive_lim_band_tbl()
130 for (k = 1; k < num_patches; k++) { in ixheaacd_derive_lim_band_tbl()
134 temp_nr_lim = nr_lim = (num_low_bnd + num_patches) - 1; in ixheaacd_derive_lim_band_tbl()
160 for (i = 0; i <= num_patches; i++) { in ixheaacd_derive_lim_band_tbl()
414 pstr_transposer_settings->num_patches = patch + 1; in ixheaacd_reset_hf_generator()
418 for (patch = 0; patch < pstr_transposer_settings->num_patches; patch++) { in ixheaacd_reset_hf_generator()
1270 ptr_frame_data->patch_param.num_patches = patch; in ixheaacd_generate_hf()
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| D | ixheaacd_env_calc.h | 50 const ia_patch_param_struct *p_str_patch_param, WORD16 num_patches,
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| D | ixheaacd_sbr_dec.c | 134 WORD32 num_patches = 0; in ixheaacd_hbe_repl_spec() local
138 num_patches++; in ixheaacd_hbe_repl_spec()
142 for (patch = (max_stretch - 1); patch < num_patches; patch++) { in ixheaacd_hbe_repl_spec()
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| D | ixheaacd_sbrdecoder.c | 209 ptr_sbr_dec->str_hf_generator.pstr_settings->num_patches, in ixheaacd_sbr_dec_reset()
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| /external/eigen/unsupported/Eigen/CXX11/src/Tensor/ |
| D | TensorPatch.h | 104 Index num_patches = 1;
110 num_patches *= (input_dims[i] - patch_dims[i] + 1);
112 m_dimensions[NumDims-1] = num_patches;
127 num_patches *= (input_dims[i] - patch_dims[i] + 1);
129 m_dimensions[0] = num_patches;
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| /external/mesa3d/src/gallium/auxiliary/draw/ |
| D | draw_tess.c | 169 unsigned num_patches = input_prim->count / shader->draw->pt.vertices_per_patch; in draw_tess_ctrl_shader_run() local
189 shader->draw->statistics.hs_invocations += num_patches; in draw_tess_ctrl_shader_run()
192 for (unsigned i = 0; i < num_patches; i++) { in draw_tess_ctrl_shader_run()
211 output_prims->primitive_count = num_patches; in draw_tess_ctrl_shader_run()
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| /external/toolchain-utils/llvm_tools/ |
| D | patch_manager.py | 297 patch_metadata_file, filesdir_path, num_patches): argument
312 '%d' % num_patches
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_pipe.h | 804 unsigned *num_patches);
807 unsigned num_patches);
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| D | evergreen_state.c | 4505 …tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches) in evergreen_setup_tess_constants() argument
4523 *num_patches = 1; in evergreen_setup_tess_constants()
4563 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0; in evergreen_setup_tess_constants()
4566 lds_size = output_patch0_offset + output_patch_size * *num_patches; in evergreen_setup_tess_constants()
4580 num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor); in evergreen_setup_tess_constants()
4602 unsigned num_patches) in evergreen_get_ls_hs_config() argument
4613 return S_028B58_NUM_PATCHES(num_patches) | in evergreen_get_ls_hs_config()
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| D | r600_state_common.c | 2063 unsigned num_patches, dirty_tex_counter, index_offset = 0; in r600_draw_vbo() local
2211 evergreen_setup_tess_constants(rctx, info, &num_patches); in r600_draw_vbo()
2251 num_patches); in r600_draw_vbo()
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| /external/tensorflow/tensorflow/core/kernels/ |
| D | eigen_spatial_convolutions_test.cc | 1532 const Index num_patches = evaluators[0].impl().dimensions()[3]; in PackRhsHelper() local
1556 Index col_offset = internal::random<Index>(0, num_patches - 10); in PackRhsHelper()
1559 Index cols = std::min(block_cols, num_patches - col_offset); in PackRhsHelper()
1573 "; num_patches=", num_patches, " patch_size=", patch_size, in PackRhsHelper()
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_instruction_selection_setup.cpp | 480 ctx->args->shader_info->tcs.num_patches = ctx->tcs_num_patches; in setup_tcs_info()
489 ctx->tcs_num_patches = ctx->args->options->key.tes.num_patches; in setup_tes_variables()
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| /external/mesa3d/src/freedreno/vulkan/ |
| D | tu_cmd_buffer.c | 3101 uint32_t num_patches = draw_count / verts_per_patch; in get_tess_param_bo_size() local
3102 return num_patches * pipeline->tess.param_stride; in get_tess_param_bo_size()
3117 uint32_t num_patches = draw_count / verts_per_patch; in get_tess_factor_bo_size() local
3132 return factor_stride * num_patches; in get_tess_factor_bo_size()
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| /external/mesa3d/docs/relnotes/ |
| D | 20.2.0.rst | 4472 - radv: remove unnecessary radv_tessellation_state::num_patches
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