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Searched refs:nxv16i32 (Results 1 – 16 of 16) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-insert-extract-tuple.ll158 …%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x …
159 …%ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %…
160 …%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 …
173 …%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x …
174 …%ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %…
175 …%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 …
188 …%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x …
189 …%ins = call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.set.nxv16i32.nxv4i32(<vscale x 16 x i32> %…
190 …%ext = call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv16i32(<vscale x 16 x i32> %ins, i32 …
203 …%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x …
[all …]
Dsve-intrinsics-ldN-reg+reg-addr-mode.ll198 define <vscale x 16 x i32> @ld4.nxv16i32(<vscale x 4 x i1> %Pg, i32 *%addr, i64 %a) {
199 ; CHECK-LABEL: ld4.nxv16i32:
203 %res = call <vscale x 16 x i32> @llvm.aarch64.sve.ld4.nxv16i32.nxv4i1.p0i32(<vscale x 4 x i1> %Pg, …
255 declare <vscale x 16 x i32> @llvm.aarch64.sve.ld4.nxv16i32.nxv4i1.p0i32(<vscale x 4 x i1>, i32*)
Dsve-split-int-reduce.ll125 %res = call i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32> %a)
223 declare i32 @llvm.vector.reduce.add.nxv16i32(<vscale x 16 x i32>)
Dsve-intrinsics-create-tuple.ll635 …%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x …
640 …%extract = tail call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv4i32.nxv16i32(<vscale x 16 …
649 …%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x …
654 …%extract = tail call <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv4i32.nxv16i32(<vscale x 16 …
778 declare <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32>, <v…
792 declare <vscale x 4 x i32> @llvm.aarch64.sve.tuple.get.nxv4i32.nxv16i32(<vscale x 16 x i32>, i32 im…
Dsve-intrinsics-ldN-reg+imm-addr-mode.ll430 define <vscale x 16 x i32> @ld4.nxv16i32(<vscale x 4 x i1> %Pg, <vscale x 4 x i32> *%addr) {
431 ; CHECK-LABEL: ld4.nxv16i32:
436 %res = call <vscale x 16 x i32> @llvm.aarch64.sve.ld4.nxv16i32.nxv4i1.p0i32(<vscale x 4 x i1> %Pg, …
491 declare <vscale x 16 x i32> @llvm.aarch64.sve.ld4.nxv16i32.nxv4i1.p0i32(<vscale x 4 x i1>, i32*)
Dsve-calling-convention-tuple-types.ll360 …%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x …
371 …%tuple = tail call <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x …
500 declare <vscale x 16 x i32> @llvm.aarch64.sve.tuple.create4.nxv16i32.nxv4i32(<vscale x 4 x i32>, <v…
Dsve-intrinsics-loads.ll493 …%res = call <vscale x 16 x i32> @llvm.aarch64.sve.ld4.nxv16i32.nxv4i1.p0i32(<vscale x 4 x i1> %pre…
564 declare <vscale x 16 x i32> @llvm.aarch64.sve.ld4.nxv16i32.nxv4i1.p0i32(<vscale x 4 x i1>, i32*)
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h175 nxv16i32 = 110, // n x 16 x i32 enumerator
493 case nxv16i32: in getVectorElementType()
595 case nxv16i32: in getVectorNumElements()
799 case nxv16i32: in getSizeInBits()
1051 if (NumElements == 16) return MVT::nxv16i32; in getScalableVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h196 nxv16i32 = 131, // n x 16 x i32 enumerator
562 case nxv16i32: in getVectorElementType()
705 case nxv16i32: in getVectorNumElements()
937 case nxv16i32: in getSizeInBits()
1260 if (NumElements == 16) return MVT::nxv16i32; in getScalableVectorVT()
/external/llvm-project/llvm/lib/Target/RISCV/Utils/
DRISCVBaseInfo.h298 constexpr MVT vint32m8_t = MVT::nxv16i32;
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.td283 // i32 N/A N/A nxv1i32 nxv2i32 nxv4i32 nxv8i32 nxv16i32
310 defvar vint32m8_t = nxv16i32;
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td141 def nxv16i32: ValueType<512, 110>; // n x 16 x i32 vector value
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp277 case MVT::nxv16i32: in getTypeForEVT()
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td163 def nxv16i32: ValueType<512, 131>; // n x 16 x i32 vector value
/external/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp430 case MVT::nxv16i32: in getTypeForEVT()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp197 case MVT::nxv16i32: return "MVT::nxv16i32"; in getEnumName()