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Searched refs:preop (Results 1 – 15 of 15) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.trig.preop.ll12 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b)
22 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7)
56 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b)
69 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7)
74 declare double @llvm.amdgcn.trig.preop.f64(double, i32) #0
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.trig.preop.ll4 declare double @llvm.amdgcn.trig.preop.f64(double, i32) nounwind readnone
15 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b) nounwind readnone
27 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7) nounwind readnone
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.trig.preop.ll4 declare double @llvm.amdgcn.trig.preop.f64(double, i32) nounwind readnone
15 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b) nounwind readnone
27 %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7) nounwind readnone
/external/tensorflow/tensorflow/core/grappler/optimizers/
Dauto_mixed_precision.cc958 Status PrintDebugLogs(bool preop, size_t timestamp);
1052 Status AutoMixedPrecisionImpl::PrintDebugLogs(bool preop, size_t timestamp) { in PrintDebugLogs() argument
1059 strings::StrCat("_", preop ? "preop" : kSuffix, "_", id_, "_", timestamp); in PrintDebugLogs()
1067 LOG(INFO) << "Saved " << (preop ? "pre-optimization" : "post-optimization") in PrintDebugLogs()
1075 LOG(INFO) << "Saved " << (preop ? "pre-optimization" : "post-optimization") in PrintDebugLogs()
1078 if (!preop) { in PrintDebugLogs()
/external/clang/test/CodeGenOpenCL/
Dbuiltins-amdgcn.cl63 // CHECK: call float @llvm.amdgcn.trig.preop.f32
70 // CHECK: call double @llvm.amdgcn.trig.preop.f64
/external/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.td157 // Special case divide preop and flags.
/external/llvm-project/clang/test/CodeGenOpenCL/
Dbuiltins-amdgcn.cl92 // CHECK: call float @llvm.amdgcn.trig.preop.f32
99 // CHECK: call double @llvm.amdgcn.trig.preop.f64
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.td236 // Special case divide preop and flags.
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUInstrInfo.td223 // Special case divide preop and flags.
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen513 amdgcn_trig_preop, // llvm.amdgcn.trig.preop
6537 "llvm.amdgcn.trig.preop",
14422 1, // llvm.amdgcn.trig.preop
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen518 amdgcn_trig_preop, // llvm.amdgcn.trig.preop
6576 "llvm.amdgcn.trig.preop",
14516 1, // llvm.amdgcn.trig.preop
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen518 amdgcn_trig_preop, // llvm.amdgcn.trig.preop
6576 "llvm.amdgcn.trig.preop",
14516 1, // llvm.amdgcn.trig.preop
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen518 amdgcn_trig_preop, // llvm.amdgcn.trig.preop
6576 "llvm.amdgcn.trig.preop",
14516 1, // llvm.amdgcn.trig.preop
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen518 amdgcn_trig_preop, // llvm.amdgcn.trig.preop
6576 "llvm.amdgcn.trig.preop",
14516 1, // llvm.amdgcn.trig.preop
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc1516 "llvm.amdgcn.trig.preop",
11649 64, // llvm.amdgcn.trig.preop