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/external/capstone/suite/MC/ARM/
Dneon-bitwise-encoding.s.cs23 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
24 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
25 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
26 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
27 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
28 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
29 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
30 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
31 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
32 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
[all …]
Dneont2-shiftaccum-encoding.s.cs6 0x88,0xef,0x54,0xe1 = vsra.s8 q7, q2, #8
14 0x88,0xff,0x5e,0x21 = vsra.u8 q1, q7, #8
15 0x9a,0xff,0x5e,0x41 = vsra.u16 q2, q7, #6
30 0x88,0xff,0x5e,0xe1 = vsra.u8 q7, q7, #8
31 0x9a,0xff,0x5e,0xe1 = vsra.u16 q7, q7, #6
47 0x90,0xff,0x5e,0xc3 = vrsra.u16 q6, q7, #16
48 0xa0,0xff,0x70,0xe3 = vrsra.u32 q7, q8, #32
63 0x90,0xff,0x5e,0xe3 = vrsra.u16 q7, q7, #16
71 0x9f,0xff,0x5e,0x45 = vsli.16 q2, q7, #15
80 0xa0,0xff,0x58,0xe4 = vsri.32 q7, q4, #32
[all …]
Dneon-shiftaccum-encoding.s.cs6 0x54,0xe1,0x88,0xf2 = vsra.s8 q7, q2, #8
14 0x5e,0x21,0x88,0xf3 = vsra.u8 q1, q7, #8
15 0x5e,0x41,0x9a,0xf3 = vsra.u16 q2, q7, #6
30 0x5e,0xe1,0x88,0xf3 = vsra.u8 q7, q7, #8
31 0x5e,0xe1,0x9a,0xf3 = vsra.u16 q7, q7, #6
47 0x5e,0xc3,0x90,0xf3 = vrsra.u16 q6, q7, #16
48 0x70,0xe3,0xa0,0xf3 = vrsra.u32 q7, q8, #32
63 0x5e,0xe3,0x90,0xf3 = vrsra.u16 q7, q7, #16
71 0x5e,0x45,0x9f,0xf3 = vsli.16 q2, q7, #15
80 0x58,0xe4,0xa0,0xf3 = vsri.32 q7, q4, #32
[all …]
/external/llvm/test/MC/ARM/
Dneon-bitwise-encoding.s110 veor q4, q7, q3
111 veor.8 q4, q7, q3
112 veor.16 q4, q7, q3
113 veor.32 q4, q7, q3
114 veor.64 q4, q7, q3
116 veor.i8 q4, q7, q3
117 veor.i16 q4, q7, q3
118 veor.i32 q4, q7, q3
119 veor.i64 q4, q7, q3
121 veor.s8 q4, q7, q3
[all …]
Dneon-shiftaccum-encoding.s7 vsra.s8 q7, q2, #8
15 vsra.u8 q1, q7, #8
16 vsra.u16 q2, q7, #6
33 vsra.u8 q7, #8
34 vsra.u16 q7, #6
42 @ CHECK: vsra.s8 q7, q2, #8 @ encoding: [0x54,0xe1,0x88,0xf2]
50 @ CHECK: vsra.u8 q1, q7, #8 @ encoding: [0x5e,0x21,0x88,0xf3]
51 @ CHECK: vsra.u16 q2, q7, #6 @ encoding: [0x5e,0x41,0x9a,0xf3]
67 @ CHECK: vsra.u8 q7, q7, #8 @ encoding: [0x5e,0xe1,0x88,0xf3]
68 @ CHECK: vsra.u16 q7, q7, #6 @ encoding: [0x5e,0xe1,0x9a,0xf3]
[all …]
Dneont2-shiftaccum-encoding.s9 vsra.s8 q7, q2, #8
17 vsra.u8 q1, q7, #8
18 vsra.u16 q2, q7, #6
35 vsra.u8 q7, #8
36 vsra.u16 q7, #6
44 @ CHECK: vsra.s8 q7, q2, #8 @ encoding: [0x88,0xef,0x54,0xe1]
52 @ CHECK: vsra.u8 q1, q7, #8 @ encoding: [0x88,0xff,0x5e,0x21]
53 @ CHECK: vsra.u16 q2, q7, #6 @ encoding: [0x9a,0xff,0x5e,0x41]
69 @ CHECK: vsra.u8 q7, q7, #8 @ encoding: [0x88,0xff,0x5e,0xe1]
70 @ CHECK: vsra.u16 q7, q7, #6 @ encoding: [0x9a,0xff,0x5e,0xe1]
[all …]
/external/llvm-project/llvm/test/MC/ARM/
Dneon-bitwise-encoding.s117 veor q4, q7, q3
118 veor.8 q4, q7, q3
119 veor.16 q4, q7, q3
120 veor.32 q4, q7, q3
121 veor.64 q4, q7, q3
123 veor.i8 q4, q7, q3
124 veor.i16 q4, q7, q3
125 veor.i32 q4, q7, q3
126 veor.i64 q4, q7, q3
128 veor.s8 q4, q7, q3
[all …]
Dmve-bitops.s99 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
100 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
101 vbic q0, q1, q7
103 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
104 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
105 vbic.s8 q0, q1, q7
107 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
108 # CHECK-NOFP: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
109 vbic.s16 q0, q1, q7
111 # CHECK: vbic q0, q1, q7 @ encoding: [0x12,0xef,0x5e,0x01]
[all …]
Dmve-qdest-qsrc.s35 # CHECK: vqdmladhx.s32 q0, q3, q7 @ encoding: [0x26,0xee,0x0e,0x1e]
36 # CHECK-NOFP: vqdmladhx.s32 q0, q3, q7 @ encoding: [0x26,0xee,0x0e,0x1e]
37 vqdmladhx.s32 q0, q3, q7
47 # CHECK: vqdmladh.s32 q1, q5, q7 @ encoding: [0x2a,0xee,0x0e,0x2e]
48 # CHECK-NOFP: vqdmladh.s32 q1, q5, q7 @ encoding: [0x2a,0xee,0x0e,0x2e]
49 vqdmladh.s32 q1, q5, q7
51 # CHECK: vqrdmladhx.s8 q0, q7, q0 @ encoding: [0x0e,0xee,0x01,0x1e]
52 # CHECK-NOFP: vqrdmladhx.s8 q0, q7, q0 @ encoding: [0x0e,0xee,0x01,0x1e]
53 vqrdmladhx.s8 q0, q7, q0
83 # CHECK: vqdmlsdhx.s8 q1, q4, q7 @ encoding: [0x08,0xfe,0x0e,0x3e]
[all …]
Dmve-float.s85 # CHECK: vcmla.f16 q3, q7, q2, #180 @ encoding: [0x2e,0xfd,0x44,0x68]
86 # CHECK-NOFP-NOT: vcmla.f16 q3, q7, q2, #180 @ encoding: [0x2e,0xfd,0x44,0x68]
87 vcmla.f16 q3, q7, q2, #180
89 # CHECK: vcmla.f16 q2, q7, q6, #270 @ encoding: [0xae,0xfd,0x4c,0x48]
90 # CHECK-NOFP-NOT: vcmla.f16 q2, q7, q6, #270 @ encoding: [0xae,0xfd,0x4c,0x48]
91 vcmla.f16 q2, q7, q6, #270
100 # CHECK: vcmla.f32 q7, q1, q3, #90 @ encoding: [0xb2,0xfc,0x46,0xe8]
101 # CHECK-NOFP-NOT: vcmla.f32 q7, q1, q3, #90 @ encoding: [0xb2,0xfc,0x46,0xe8]
102 vcmla.f32 q7, q1, q3, #90
108 # CHECK: vcmla.f32 q3, q2, q7, #270 @ encoding: [0xb4,0xfd,0x4e,0x68]
[all …]
Dmve-integer.s59 # CHECK: vmul.i32 q7, q3, q6 @ encoding: [0x26,0xef,0x5c,0xe9]
60 vmul.i32 q7, q3, q6
110 # CHECK: vqsub.u16 q0, q7, q1 @ encoding: [0x1e,0xff,0x52,0x02]
111 vqsub.u16 q0, q7, q1
113 # CHECK: vqsub.u32 q1, q4, q7 @ encoding: [0x28,0xff,0x5e,0x22]
114 vqsub.u32 q1, q4, q7
152 # CHECK: vabd.u32 q0, q7, q4 @ encoding: [0x2e,0xff,0x48,0x07]
153 vabd.u32 q0, q7, q4
185 # CHECK: vhsub.u16 q0, q7, q5 @ encoding: [0x1e,0xff,0x4a,0x02]
186 vhsub.u16 q0, q7, q5
[all …]
Dneont2-shiftaccum-encoding.s9 vsra.s8 q7, q2, #8
17 vsra.u8 q1, q7, #8
18 vsra.u16 q2, q7, #6
35 vsra.u8 q7, #8
36 vsra.u16 q7, #6
44 @ CHECK: vsra.s8 q7, q2, #8 @ encoding: [0x88,0xef,0x54,0xe1]
52 @ CHECK: vsra.u8 q1, q7, #8 @ encoding: [0x88,0xff,0x5e,0x21]
53 @ CHECK: vsra.u16 q2, q7, #6 @ encoding: [0x9a,0xff,0x5e,0x41]
69 @ CHECK: vsra.u8 q7, q7, #8 @ encoding: [0x88,0xff,0x5e,0xe1]
70 @ CHECK: vsra.u16 q7, q7, #6 @ encoding: [0x9a,0xff,0x5e,0xe1]
[all …]
Dneon-shiftaccum-encoding.s7 vsra.s8 q7, q2, #8
15 vsra.u8 q1, q7, #8
16 vsra.u16 q2, q7, #6
33 vsra.u8 q7, #8
34 vsra.u16 q7, #6
42 @ CHECK: vsra.s8 q7, q2, #8 @ encoding: [0x54,0xe1,0x88,0xf2]
50 @ CHECK: vsra.u8 q1, q7, #8 @ encoding: [0x5e,0x21,0x88,0xf3]
51 @ CHECK: vsra.u16 q2, q7, #6 @ encoding: [0x5e,0x41,0x9a,0xf3]
67 @ CHECK: vsra.u8 q7, q7, #8 @ encoding: [0x5e,0xe1,0x88,0xf3]
68 @ CHECK: vsra.u16 q7, q7, #6 @ encoding: [0x5e,0xe1,0x9a,0xf3]
[all …]
/external/llvm/test/CodeGen/ARM/
Dthumb-big-stack.ll145 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
147 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
149 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
151 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
153 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
155 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
157 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
159 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
161 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
163 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dthumb-big-stack.ll145 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
147 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
149 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
151 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
153 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
155 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
157 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
159 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
161 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
163 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q…
[all …]
/external/libavc/common/arm/
Dih264_inter_pred_luma_horz_qpel_vert_hpel_a9q.s329 vaddl.u8 q7, d4, d6
332 vmla.u16 q6, q7, q13
334 vaddl.u8 q7, d1, d11
336 vmla.u16 q7, q9, q13
340 vmls.u16 q7, q11, q12
343 vext.16 q11, q6, q7, #5
347 vst1.32 {q7}, [r9], r7 @ store row 0 to temp buffer: col 1
349 vext.16 q8, q6, q7, #2
351 vext.16 q9, q6, q7, #3
352 vext.16 q10, q6, q7, #4
[all …]
Dih264_inter_pred_filters_luma_horz_a9q.s131 vaddl.u8 q7, d28, d5 @// a0 + a5 (column1,row1)
139 vmlal.u8 q7, d28, d1 @// a0 + a5 + 20a2 (column1,row1)
147 vmlal.u8 q7, d28, d1 @// a0 + a5 + 20a2 + 20a3 (column1,row1)
155 vmlsl.u8 q7, d28, d0 @// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row1)
163 vmlsl.u8 q7, d28, d0 @// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column1,row1)
169 …vqrshrun.s16 d23, q7, #5 @// (a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 + 16) >> 5 (column1,r…
188 vaddl.u8 q7, d28, d5 @// a0 + a5 (column1,row1)
190 vmlal.u8 q7, d25, d1 @// a0 + a5 + 20a2 (column1,row1)
191 vmlal.u8 q7, d24, d1 @// a0 + a5 + 20a2 + 20a3 (column1,row1)
192 vmlsl.u8 q7, d23, d0 @// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row1)
[all …]
/external/rust/crates/ring/crypto/curve25519/asm/
Dx25519-asm-arm.S42 vpush {q4,q5,q6,q7}
113 vshr.u64 q7,q7,#29
125 vand q7,q7,q3
152 vadd.i64 q7,q7,q12
154 vadd.i64 q15,q7,q0
168 vsub.i64 q7,q7,q12
179 vsub.i64 q7,q8,q12
196 vshl.i64 q7,q8,#26
201 vsub.i64 q3,q6,q7
262 veor q10,q7,q9
[all …]
/external/rust/crates/quiche/deps/boringssl/src/crypto/curve25519/asm/
Dx25519-asm-arm.S40 vpush {q4,q5,q6,q7}
111 vshr.u64 q7,q7,#29
123 vand q7,q7,q3
150 vadd.i64 q7,q7,q12
152 vadd.i64 q15,q7,q0
166 vsub.i64 q7,q7,q12
177 vsub.i64 q7,q8,q12
194 vshl.i64 q7,q8,#26
199 vsub.i64 q3,q6,q7
260 veor q10,q7,q9
[all …]
/external/boringssl/src/crypto/curve25519/asm/
Dx25519-asm-arm.S40 vpush {q4,q5,q6,q7}
111 vshr.u64 q7,q7,#29
123 vand q7,q7,q3
150 vadd.i64 q7,q7,q12
152 vadd.i64 q15,q7,q0
166 vsub.i64 q7,q7,q12
177 vsub.i64 q7,q8,q12
194 vshl.i64 q7,q8,#26
199 vsub.i64 q3,q6,q7
260 veor q10,q7,q9
[all …]
/external/libhevc/common/arm/
Dihevc_inter_pred_luma_vert_w16inp_w16out.s210 vmull.s16 q7,d4,d23
211 vmlal.s16 q7,d3,d22
212 vmlal.s16 q7,d5,d24
213 vmlal.s16 q7,d6,d25
215 vmlal.s16 q7,d7,d26
217 vmlal.s16 q7,d16,d27
219 vmlal.s16 q7,d17,d28
221 vmlal.s16 q7,d18,d29
250 vsub.s32 q7, q7, q15
269 vshrn.s32 d14, q7, #6
[all …]
Dihevc_inter_pred_filters_luma_vert_w16inp.s199 vmull.s16 q7,d4,d23
200 vmlal.s16 q7,d3,d22
201 vmlal.s16 q7,d5,d24
202 vmlal.s16 q7,d6,d25
204 vmlal.s16 q7,d7,d26
206 vmlal.s16 q7,d16,d27
208 vmlal.s16 q7,d17,d28
210 vmlal.s16 q7,d18,d29
237 vqshrn.s32 d14, q7, #6
255 vqrshrun.s16 d14,q7,#6
[all …]
/external/libvpx/libvpx/vp8/common/arm/neon/
Dvp8_loopfilter_neon.c24 uint8x16_t q7, // q0 in vp8_loop_filter_neon() argument
41 q14u8 = vabdq_u8(q8, q7); in vp8_loop_filter_neon()
50 q9 = vabdq_u8(q6, q7); in vp8_loop_filter_neon()
66 q7 = veorq_u8(q7, q10); in vp8_loop_filter_neon()
75 q2s16 = vsubl_s8(vget_low_s8(vreinterpretq_s8_u8(q7)), in vp8_loop_filter_neon()
77 q11s16 = vsubl_s8(vget_high_s8(vreinterpretq_s8_u8(q7)), in vp8_loop_filter_neon()
111 q10s8 = vqsubq_s8(vreinterpretq_s8_u8(q7), q1s8); in vp8_loop_filter_neon()
132 uint8x16_t q5, q6, q7, q8, q9, q10; in vp8_loop_filter_horizontal_edge_y_neon() local
147 q7 = vld1q_u8(src); in vp8_loop_filter_horizontal_edge_y_neon()
155 vp8_loop_filter_neon(qblimit, qlimit, qthresh, q3, q4, q5, q6, q7, q8, q9, in vp8_loop_filter_horizontal_edge_y_neon()
[all …]
Dmbloopfilter_neon.c23 uint8x16_t q7, // q0 in vp8_mbloop_filter_neon() argument
43 q14u8 = vabdq_u8(q8, q7); in vp8_mbloop_filter_neon()
52 q12u8 = vabdq_u8(q6, q7); in vp8_mbloop_filter_neon()
69 q7 = veorq_u8(q7, q0u8); in vp8_mbloop_filter_neon()
80 q2s16 = vsubl_s8(vget_low_s8(vreinterpretq_s8_u8(q7)), in vp8_mbloop_filter_neon()
82 q13s16 = vsubl_s8(vget_high_s8(vreinterpretq_s8_u8(q7)), in vp8_mbloop_filter_neon()
110 q7s8 = vqsubq_s8(vreinterpretq_s8_u8(q7), q2s8); in vp8_mbloop_filter_neon()
160 uint8x16_t q5, q6, q7, q8, q9, q10; in vp8_mbloop_filter_horizontal_edge_y_neon() local
176 q7 = vld1q_u8(src); in vp8_mbloop_filter_horizontal_edge_y_neon()
184 vp8_mbloop_filter_neon(qblimit, qlimit, qthresh, q3, q4, q5, q6, q7, q8, q9, in vp8_mbloop_filter_horizontal_edge_y_neon()
[all …]
/external/XNNPACK/src/f32-gemm/gen/
D4x8-minmax-aarch32-neon-cortex-a75.S126 VMLA.F32 q9, q7, d0[1]
127 VMLA.F32 q11, q7, d1[1]
128 VMLA.F32 q13, q7, d2[1]
129 VMLA.F32 q15, q7, d3[1]
149 VMLA.F32 q9, q7, d4[1]
150 VMLA.F32 q11, q7, d5[1]
152 VMLA.F32 q13, q7, d6[1]
153 VMLA.F32 q15, q7, d7[1]
176 VMLA.F32 q9, q7, d0[1]
177 VMLA.F32 q11, q7, d1[1]
[all …]

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