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/external/libffi/src/ia64/
Dunix.S58 add r16 = 16, in0
65 ldf.fill f9 = [r16], 32
68 ldf.fill f11 = [r16], 32
71 ldf.fill f13 = [r16], 32
74 ldf.fill f15 = [r16], 24
77 ld8 out1 = [r16], 16
80 ld8 out3 = [r16], 16
83 ld8 out5 = [r16], 16
86 ld8 out7 = [r16]
93 ld8 r16 = [in2], 8
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/ia64/
Dunix.S58 add r16 = 16, in0
65 ldf.fill f9 = [r16], 32
68 ldf.fill f11 = [r16], 32
71 ldf.fill f13 = [r16], 32
74 ldf.fill f15 = [r16], 24
77 ld8 out1 = [r16], 16
80 ld8 out3 = [r16], 16
83 ld8 out5 = [r16], 16
86 ld8 out7 = [r16]
93 ld8 r16 = [in2], 8
[all …]
/external/llvm-project/llvm/test/MC/Hexagon/
Dparse-pound-hi.s37 r16.h = #HI(0x405000)
38 #CHECK: 7230c040 { r16.h = #64 }
39 r16.h = #HI (0x405000)
40 #CHECK: 7230c040 { r16.h = #64 }
41 r16.h = #hi(0x405000)
42 #CHECK: 7230c040 { r16.h = #64 }
43 r16.h = #hi (0x405000)
44 #CHECK: 7230c040 { r16.h = #64 }
45 r16.l = #LO(0x405020)
46 #CHECK: 7170d020 { r16.l = #20512 }
[all …]
/external/llvm-project/llvm/test/MC/AVR/
Dinst-fmul.s7 fmul r22, r16
11 fmul r16, r16
12 fmul r16, r23
14 ; CHECK: fmul r22, r16 ; encoding: [0x68,0x03]
18 ; CHECK: fmul r16, r16 ; encoding: [0x08,0x03]
19 ; CHECK: fmul r16, r23 ; encoding: [0x0f,0x03]
21 ; CHECK-INST: fmul r22, r16
25 ; CHECK-INST: fmul r16, r16
26 ; CHECK-INST: fmul r16, r23
Dinst-muls.s7 muls r22, r16
11 muls r16, r16
12 muls r16, r31
14 ; CHECK: muls r22, r16 ; encoding: [0x60,0x02]
18 ; CHECK: muls r16, r16 ; encoding: [0x00,0x02]
19 ; CHECK: muls r16, r31 ; encoding: [0x0f,0x02]
21 ; CHECK-INST: muls r22, r16
25 ; CHECK-INST: muls r16, r16
26 ; CHECK-INST: muls r16, r31
Drelocations.s40 ldi r16, +lo8(abc)
41 ldi r16, lo8(+(abc))
47 ldi r16, +hi8(abc)
48 ldi r16, hi8(+(abc))
52 ldi r16, -lo8(abc)
53 ldi r16, lo8(-(abc))
57 ldi r16, -hi8(abc)
58 ldi r16, hi8(-(abc))
63 ldi r16, hh8(foo)
64 ldi r16, +hh8(foo)
[all …]
Dinst-and.s9 and r16, r31
10 and r31, r16
14 ; CHECK: and r16, r31 ; encoding: [0x0f,0x23]
15 ; CHECK: and r31, r16 ; encoding: [0xf0,0x23]
19 ; CHECK-INST: and r16, r31
20 ; CHECK-INST: and r31, r16
Dinst-sbc.s9 sbc r16, r31
10 sbc r31, r16
14 ; CHECK: sbc r16, r31 ; encoding: [0x0f,0x0b]
15 ; CHECK: sbc r31, r16 ; encoding: [0xf0,0x0b]
19 ; CHECK-INST: sbc r16, r31
20 ; CHECK-INST: sbc r31, r16
Dinst-sub.s8 sub r16, r31
9 sub r31, r16
13 ; CHECK: sub r16, r31 ; encoding: [0x0f,0x1b]
14 ; CHECK: sub r31, r16 ; encoding: [0xf0,0x1b]
18 ; CHECK-INST: sub r16, r31
19 ; CHECK-INST: sub r31, r16
Dinst-adc.s9 adc r16, r31
10 adc r31, r16
14 ; CHECK: adc r16, r31 ; encoding: [0x0f,0x1f]
15 ; CHECK: adc r31, r16 ; encoding: [0xf0,0x1f]
19 ; CHECK-INST: adc r16, r31
20 ; CHECK-INST: adc r31, r16
Dinst-add.s9 add r16, r31
10 add r31, r16
14 ; CHECK: add r16, r31 ; encoding: [0x0f,0x0f]
15 ; CHECK: add r31, r16 ; encoding: [0xf0,0x0f]
19 ; CHECK-INST: add r16, r31
20 ; CHECK-INST: add r31, r16
Dinst-eor.s9 eor r16, r31
10 eor r31, r16
14 ; CHECK: eor r16, r31 ; encoding: [0x0f,0x27]
15 ; CHECK: eor r31, r16 ; encoding: [0xf0,0x27]
19 ; CHECK-INST: eor r16, r31
20 ; CHECK-INST: eor r31, r16
Dinst-or.s8 or r16, r31
9 or r31, r16
13 ; CHECK: or r16, r31 ; encoding: [0x0f,0x2b]
14 ; CHECK: or r31, r16 ; encoding: [0xf0,0x2b]
18 ; CHECK-INST: or r16, r31
19 ; CHECK-INST: or r31, r16
Dsyntax-reg-int-literal.s7 add r16, r31
8 add 31, r16
13 ; CHECK: add r16, r31 ; encoding: [0x0f,0x0f]
14 ; CHECK: add r16, r31 ; encoding: [0x0f,0x0f]
15 ; CHECK: add r31, r16 ; encoding: [0xf0,0x0f]
Dinst-mul.s7 mul r16, r31
8 mul r31, r16
12 ; CHECK: mul r16, r31 ; encoding: [0x0f,0x9f]
13 ; CHECK: mul r31, r16 ; encoding: [0xf0,0x9f]
/external/skqp/src/compute/hs/cuda/sm_35/u32/
Dhs_cuda_u32.cu45 HS_KEY_TYPE r16 = HS_SLAB_GLOBAL_LOAD(vin, 15); variable
53 HS_CMP_XCHG(r15, r16);
61 HS_CMP_XCHG(r14, r16);
69 HS_CMP_XCHG(r12, r16);
77 HS_CMP_XCHG(r8, r16);
108 HS_CMP_FLIP(0, r1, r16);
134 HS_CMP_XCHG(r8, r16);
136 HS_CMP_XCHG(r12, r16);
140 HS_CMP_XCHG(r14, r16);
148 HS_CMP_XCHG(r15, r16);
[all …]
/external/skqp/src/compute/hs/cl/intel/gen8/u64/
Dhs_kernels.cl36 HS_KEY_TYPE r16 = HS_SLAB_GLOBAL_LOAD(vin, 15);
44 HS_CMP_XCHG(r15, r16);
52 HS_CMP_XCHG(r14, r16);
60 HS_CMP_XCHG(r12, r16);
68 HS_CMP_XCHG(r8, r16);
99 HS_CMP_FLIP(0, r1, r16);
125 HS_CMP_XCHG(r8, r16);
127 HS_CMP_XCHG(r12, r16);
131 HS_CMP_XCHG(r14, r16);
139 HS_CMP_XCHG(r15, r16);
[all …]
Dhs_kernels.pre.cl25 ulong r16 = vin[gmem_idx + (1 << 3) * 15];
61 if (r15 >= r16) {
63 r15 = r16;
64 r16 = t;
101 if (r14 >= r16) {
103 r14 = r16;
104 r16 = t;
141 if (r12 >= r16) {
143 r12 = r16;
144 r16 = t;
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dlivephysregs-lane-masks.mir4 # CHECK: $p0 = C2_cmpeqi $r16, 0
21 liveins: $r0, $r16
23 $p0 = C2_cmpeqi $r16, 0
31 liveins: $d0:0x00000002, $d15:0x00000001, $r16
34 S2_storeri_io killed $r16, 0, $r1
Dopt-glob-addrs-000.ll6 ; CHECK-DAG: r16 = ##.Lg0+32767
12 ; CHECK-DAG: r0 = add(r16,#-32767)
19 ; CHECK-DAG: r0 = add(r16,#-32767)
26 ; CHECK-DAG: r0 = add(r16,#-32767)
33 ; CHECK-DAG: r0 = add(r16,#-32767)
40 ; CHECK-DAG: r0 = add(r16,#-32767)
47 ; CHECK-DAG: r0 = add(r16,#-32767)
54 ; CHECK-DAG: r0 = add(r16,#-32767)
61 ; CHECK-DAG: r0 = add(r16,#-32767)
68 ; CHECK-DAG: r0 = add(r16,#-32767)
[all …]
Danti-dep-partial.mir16 liveins: $r0, $r1, $d1, $d2, $r16, $r17, $r19, $r22, $r23
18 $r6 = M2_mpyi $r16, $r16
21 $r3 = A2_tfr killed $r16
/external/llvm/test/CodeGen/MIR/Hexagon/
Danti-dep-partial.mir17 liveins: %r0, %r1, %d1, %d2, %r16, %r17, %r19, %r22, %r23
19 %r6 = M2_mpyi %r16, %r16
22 %r3 = A2_tfr killed %r16
/external/python/cpython2/Modules/_ctypes/libffi/src/nios2/
Dsysv.S51 stw r16, 0(sp)
57 mov r16, r7
77 callr r16
83 ldw r16, 0(sp)
/external/libffi/src/nios2/
Dsysv.S51 stw r16, 0(sp)
57 mov r16, r7
77 callr r16
83 ldw r16, 0(sp)
/external/linux-kselftest/tools/testing/selftests/powerpc/pmu/ebb/
Dbusy_loop.S14 std r16, 144(%r1)
53 li r16, 0x1616
54 std r16, -184(%r1)
113 cmpwi r16, 0x1616
158 li r16, 0xef
206 ld r16, -184(%r1)
207 cmpwi r16, 0x1616
254 ld r16, 144(%r1)

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