/external/mesa3d/src/amd/vulkan/ |
D | si_cmd_buffer.c | 119 radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0); in si_emit_compute() 120 radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0); in si_emit_compute() 121 radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0); in si_emit_compute() 122 radeon_set_sh_reg(cs, R_00B89C_COMPUTE_USER_ACCUM_3, 0); in si_emit_compute() 123 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0); in si_emit_compute() 124 radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0); in si_emit_compute() 136 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, in si_emit_compute() 317 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, in si_emit_graphics() 319 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, in si_emit_graphics() 321 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, in si_emit_graphics() [all …]
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D | radv_sqtt.c | 202 radeon_set_sh_reg(cs, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, in radv_emit_thread_trace_start() 280 radeon_set_sh_reg(cs, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, in radv_emit_thread_trace_stop()
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D | radv_cs.h | 106 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg() function
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D | radv_pipeline.c | 4280 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2); in radv_pipeline_generate_hw_ls() 5361 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, shader->config.rsrc3); in radv_pipeline_generate_hw_cs() 5387 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, in radv_pipeline_generate_compute_state()
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D | radv_cmd_buffer.c | 2970 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, in radv_flush_ngg_gs_state() 5048 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index); in radv_emit_view_index() 5055 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index); in radv_emit_view_index()
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D | radv_device.c | 3463 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE, in radv_emit_compute_scratch()
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/external/mesa3d/src/gallium/drivers/radeonsi/ |
D | si_compute.c | 366 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, 0x190 /* Default value */); in si_emit_initial_compute_regs() 380 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_PERFCOUNT_ENABLE, 0); in si_emit_initial_compute_regs() 381 radeon_set_sh_reg(cs, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, 0); in si_emit_initial_compute_regs() 400 radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0); in si_emit_initial_compute_regs() 401 radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0); in si_emit_initial_compute_regs() 402 radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0); in si_emit_initial_compute_regs() 403 radeon_set_sh_reg(cs, R_00B89C_COMPUTE_USER_ACCUM_3, 0); in si_emit_initial_compute_regs() 404 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0); in si_emit_initial_compute_regs() 405 radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0); in si_emit_initial_compute_regs() 524 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE, in si_switch_compute_shader() [all …]
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D | si_state_draw.c | 257 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2); in si_emit_derived_tess_state() 274 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2); in si_emit_derived_tess_state() 615 radeon_set_sh_reg( in si_emit_vs_state() 625 radeon_set_sh_reg(cs, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_VS_STATE_BITS * 4, in si_emit_vs_state() 632 radeon_set_sh_reg(cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + SI_SGPR_VS_STATE_BITS * 4, in si_emit_vs_state() 974 radeon_set_sh_reg(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, draws[i].start); in si_emit_draw_packets()
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D | si_compute_prim_discard.c | 1215 radeon_set_sh_reg( in si_dispatch_prim_discard_cs_and_draw() 1391 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, in si_dispatch_prim_discard_cs_and_draw() 1495 radeon_set_sh_reg(cs, R_00B810_COMPUTE_START_X, start_block); in si_dispatch_prim_discard_cs_and_draw() 1496 radeon_set_sh_reg(cs, R_00B81C_COMPUTE_NUM_THREAD_X, in si_dispatch_prim_discard_cs_and_draw()
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D | si_build_pm4.h | 99 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg() function
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D | si_state_viewport.c | 106 radeon_set_sh_reg(sctx->gfx_cs, R_00B220_SPI_SHADER_PGM_LO_GS, in si_emit_cull_state()
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/external/mesa3d/src/gallium/drivers/r600/ |
D | r600_cs.h | 178 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg() function
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