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Searched refs:rail_name (Results 1 – 10 of 10) sorted by relevance

/external/perfetto/src/android_internal/
Dpower_stats.cc167 strncpy(descriptor.rail_name, rail_info.railName.c_str(), in GetAvailableRails()
168 sizeof(descriptor.rail_name)); in GetAvailableRails()
171 descriptor.rail_name[sizeof(descriptor.rail_name) - 1] = '\0'; in GetAvailableRails()
266 strncpy(cur.rail_name, result.name.c_str(), sizeof(cur.rail_name)); in GetAvailableRails()
268 cur.rail_name[sizeof(cur.rail_name) - 1] = '\0'; in GetAvailableRails()
Dpower_stats.h38 char rail_name[64]; member
/external/perfetto/test/trace_processor/power/
Dpower_rails_well_known.textproto5 rail_name: "S3M_VDD_CPUCL1"
26 rail_name: "S2S_VDD_G3D"
Dpower_rails.textproto5 rail_name: "test_rail"
26 rail_name: "test_rail2"
Dpower_rails_custom_clock.textproto18 rail_name: "test_rail"
/external/perfetto/src/trace_processor/importers/proto/
Dandroid_probes_module.cc118 const char* friendly_name = MapToFriendlyPowerRailName(desc.rail_name()); in TokenizePacket()
124 writer.AppendStringView(desc.rail_name()); in TokenizePacket()
/external/perfetto/protos/perfetto/trace/power/
Dpower_rails.proto27 optional string rail_name = 2; field
/external/perfetto/src/traced/probes/power/
Dandroid_power_data_source.cc271 rail_desc_proto->set_rail_name(rail_descriptor.rail_name); in WritePowerRailsData()
/external/perfetto/test/
Dsynth_common.py230 descriptor.rail_name = name
/external/perfetto/protos/perfetto/trace/
Dperfetto_trace.proto7623 optional string rail_name = 2; field