| /external/perfetto/src/trace_processor/rpc/ |
| D | proto_ring_buffer.cc | 85 PERFETTO_DCHECK(wr_ >= rd_); in Append()
90 if (rd_ == wr_) in Append()
91 rd_ = wr_ = 0; in Append()
95 if (rd_ == wr_) { in Append()
122 memmove(&buf[0], &buf[rd_], wr_ - rd_); in Append()
123 avail += rd_; in Append()
124 wr_ -= rd_; in Append()
125 rd_ = 0; in Append()
160 PERFETTO_CHECK(rd_ == wr_); in ReadMessage()
168 PERFETTO_DCHECK(rd_ <= wr_); in ReadMessage()
[all …]
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| D | proto_ring_buffer.h | 126 size_t avail() const { return buf_.size() - (wr_ - rd_); } in avail()
132 size_t rd_ = 0; // Offset of the read cursor in |buf_|. variable
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| /external/tensorflow/tensorflow/compiler/xla/service/cpu/ |
| D | shape_partition_test.cc | 152 : generator_(rd_()), distribution_(1, 10) {} in RandomShapePartitionIteratorTest()
158 std::random_device rd_; member in xla::cpu::__anon485538070111::RandomShapePartitionIteratorTest
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| /external/rust/crates/grpcio-sys/grpc/third_party/cares/cares/test/ |
| D | dns-proto.h | 189 aa_(false), tc_(false), rd_(false), ra_(false), in DNSPacket()
213 DNSPacket& set_rd(bool v = true) { rd_ = v; return *this; }
228 bool rd_; member
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| D | dns-proto.cc | 600 if (rd_) b |= 0x01; in data()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.td | 426 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
430 let Constraints = "$rd = $rd_";
450 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
456 let Constraints = "$rd = $rd_";
473 MipsPseudo16<(outs CPU16Regs:$rd_),
480 let Constraints = "$rd = $rd_";
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.td | 425 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
429 let Constraints = "$rd = $rd_";
449 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
455 let Constraints = "$rd = $rd_";
472 MipsPseudo16<(outs CPU16Regs:$rd_),
479 let Constraints = "$rd = $rd_";
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.td | 425 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
429 let Constraints = "$rd = $rd_";
449 MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
455 let Constraints = "$rd = $rd_";
472 MipsPseudo16<(outs CPU16Regs:$rd_),
479 let Constraints = "$rd = $rd_";
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenGlobalISel.inc | 17473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
17501 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18571 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18600 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18658 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
18716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
[all …]
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