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Searched refs:reg12 (Results 1 – 9 of 9) sorted by relevance

/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c16 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
22 LD_SH8(input, 16, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15); in vpx_idct16_1d_rows_msa()
26 TRANSPOSE8x8_SH_SH(reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15, reg8, in vpx_idct16_1d_rows_msa()
27 reg9, reg10, reg11, reg12, reg13, reg14, reg15); in vpx_idct16_1d_rows_msa()
33 DOTP_CONST_PAIR(reg4, reg12, cospi_24_64, cospi_8_64, reg4, reg12); in vpx_idct16_1d_rows_msa()
34 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vpx_idct16_1d_rows_msa()
35 SUB4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg0, reg12, reg4, in vpx_idct16_1d_rows_msa()
87 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vpx_idct16_1d_rows_msa()
92 reg12 = tmp5; in vpx_idct16_1d_rows_msa()
97 TRANSPOSE8x8_SH_SH(reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14, reg0, in vpx_idct16_1d_rows_msa()
[all …]
/external/elfutils/tests/
Drun-varlocs.sh72 [400528,400529) {reg12}
573 [40106e,401086) {reg12}
Drun-addrcfi.sh45 x87 reg12 (%st1): undefined
92 x87 reg12 (%st1): undefined
144 integer reg12 (%r12): same_value
210 integer reg12 (%r12): same_value
314 integer reg12 (r12): undefined
1336 integer reg12 (r12): undefined
2364 integer reg12 (r12): undefined
3390 integer reg12 (%r12): same_value
3467 integer reg12 (%r12): same_value
3545 integer reg12 (r12): undefined
[all …]
Drun-readelf-loc.sh1100 [ 0] reg12
/external/libaom/libaom/av1/common/arm/
Dconvolve_neon.c1169 reg10, reg11, reg12, reg13, reg14; in av1_convolve_2d_sr_neon() local
1207 reg12 = vget_high_s16(vreinterpretq_s16_u16(vmovl_u8(t1))); in av1_convolve_2d_sr_neon()
1226 d5 = convolve8_4x4(reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg12, in av1_convolve_2d_sr_neon()
1229 d6 = convolve8_4x4(reg6, reg7, reg8, reg9, reg10, reg11, reg12, reg13, in av1_convolve_2d_sr_neon()
1232 d7 = convolve8_4x4(reg7, reg8, reg9, reg10, reg11, reg12, reg13, reg14, in av1_convolve_2d_sr_neon()
1256 reg4 = reg12; in av1_convolve_2d_sr_neon()
/external/llvm/include/llvm/Support/
DDwarf.def213 HANDLE_DW_OP(0x5c, reg12)
/external/llvm-project/llvm/test/tools/llvm-readobj/ELF/
Dunwind.test160 # CHECK-NEXT: DW_CFA_offset: reg12 -48
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/BinaryFormat/
DDwarf.def567 HANDLE_DW_OP(0x5c, reg12, 2, DWARF)
/external/llvm-project/llvm/include/llvm/BinaryFormat/
DDwarf.def585 HANDLE_DW_OP(0x5c, reg12, 2, DWARF)