Searched refs:regValue (Results 1 – 8 of 8) sorted by relevance
155 UINT_32 regValue, TileConfig* pCfg) const;158 UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
436 const ADDR_REGISTER_VALUE* pRegValue = &pCreateIn->regValue; in HwlInitGlobalParams()1582 UINT_32 regValue, ///< [in] GB_TILE_MODE register in ReadGbTileMode() argument1587 gbTileMode.val = regValue; in ReadGbTileMode()1732 UINT_32 regValue, ///< [in] GB_MACRO_TILE_MODE register in ReadGbMacroTileCfg() argument1737 gbTileMode.val = regValue; in ReadGbMacroTileCfg()
338 VOID ReadGbTileMode(UINT_32 regValue, TileConfig* pCfg) const;
2368 const ADDR_REGISTER_VALUE* pRegValue = &pCreateIn->regValue; in HwlInitGlobalParams()3074 UINT_32 regValue, ///< [in] GB_TILE_MODE register in ReadGbTileMode() argument3079 gbTileMode.val = regValue; in ReadGbTileMode()
345 ADDR_REGISTER_VALUE regValue = {0}; in ac_addrlib_create() local353 regValue.gbAddrConfig = amdinfo->gb_addr_cfg; in ac_addrlib_create()365 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3; in ac_addrlib_create()366 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2; in ac_addrlib_create()368 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask; in ac_addrlib_create()369 regValue.pTileConfig = amdinfo->gb_tile_mode; in ac_addrlib_create()370 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode); in ac_addrlib_create()372 regValue.pMacroTileConfig = NULL; in ac_addrlib_create()373 regValue.noOfMacroEntries = 0; in ac_addrlib_create()375 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode; in ac_addrlib_create()[all …]
373 ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data member
772 gbAddrConfig.u32All = pCreateIn->regValue.gbAddrConfig; in HwlInitGlobalParams()
1049 gbAddrConfig.u32All = pCreateIn->regValue.gbAddrConfig; in HwlInitGlobalParams()