| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_blit.c | 243 float reg_width, float reg_height, in calc_tex_coords() argument
247 buf[1] = buf[0] + reg_width / img_width; in calc_tex_coords()
261 unsigned reg_width, unsigned reg_height, in emit_draw_packet() argument
270 reg_width, reg_height, in emit_draw_packet()
278 verts[4] = dst_x_offset + reg_width; in emit_draw_packet()
283 verts[8] = dst_x_offset + reg_width; in emit_draw_packet()
341 unsigned reg_width, in r100_blit() argument
358 if (reg_width + src_x_offset > src_width) in r100_blit()
359 reg_width = src_width - src_x_offset; in r100_blit()
362 if (reg_width + dst_x_offset > dst_width) in r100_blit()
[all …]
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| D | radeon_common_context.h | 459 unsigned reg_width,
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_blit.c | 394 float reg_width, float reg_height, argument
398 buf[1] = buf[0] + reg_width / img_width;
412 unsigned reg_width, unsigned reg_height, argument
421 reg_width, reg_height,
429 verts[4] = dst_x_offset + reg_width;
434 verts[8] = dst_x_offset + reg_width;
489 unsigned reg_width, argument
506 if (reg_width + src_x_offset > src_width)
507 reg_width = src_width - src_x_offset;
510 if (reg_width + dst_x_offset > dst_width)
[all …]
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| D | radeon_common_context.h | 459 unsigned reg_width,
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| /external/llvm-project/libcxx/test/std/experimental/simd/simd.abi/ |
| D | vector_extension.pass.cpp | 22 constexpr inline int reg_width() { in reg_width() function
54 ex::__simd_abi<ex::_StorageKind::_VecExt, reg_width()>>::value,
59 ex::__simd_abi<ex::_StorageKind::_Array, reg_width()>>::value,
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| /external/libcxx/test/std/experimental/simd/simd.abi/ |
| D | vector_extension.pass.cpp | 21 constexpr inline int reg_width() { in reg_width() function
53 ex::__simd_abi<ex::_StorageKind::_VecExt, reg_width()>>::value,
58 ex::__simd_abi<ex::_StorageKind::_Array, reg_width()>>::value,
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_fs_reg_allocate.cpp | 50 int reg_width = dispatch_width / 8; in assign_regs_trivial() local
53 hw_reg_mapping[0] = ALIGN(this->first_non_payload_grf, reg_width); in assign_regs_trivial()
433 int reg_width = fs->dispatch_width / 8; in fs_reg_alloc() local
434 rsi = util_logbase2(reg_width); in fs_reg_alloc()
435 payload_node_count = ALIGN(fs->first_non_payload_grf, reg_width); in fs_reg_alloc()
525 int reg_width = v->dispatch_width / 8; in get_used_mrfs() local
533 if (reg_width == 2) { in get_used_mrfs()
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| D | brw_fs_visitor.cpp | 96 int reg_width = dispatch_width / 8; in emit_dummy_fs() local
101 bld.MOV(fs_reg(MRF, 2 + i * reg_width, BRW_REGISTER_TYPE_F), in emit_dummy_fs()
111 write->mlen = 4 * reg_width; in emit_dummy_fs()
115 write->mlen = 2 + 4 * reg_width; in emit_dummy_fs()
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| D | brw_fs_copy_propagation.cpp | 624 const unsigned reg_width = REG_SIZE / (type_sz(inst->src[arg].type) * in try_copy_propagate() local
626 inst->src[arg].width = cvt(MIN2(orig_width, reg_width)) - 1; in try_copy_propagate()
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| D | brw_fs.cpp | 1189 int reg_width = dispatch_width / 8; in vgrf() local
1191 alloc.allocate(glsl_count_dword_slots(type, false) * reg_width), in vgrf()
4950 unsigned reg_width = bld.dispatch_width() / 8; in lower_sampler_logical_send_gen7() local
4981 if (!inst->eot && regs_written(inst) != 4 * reg_width) { in lower_sampler_logical_send_gen7()
4982 assert(regs_written(inst) % reg_width == 0); in lower_sampler_logical_send_gen7()
4983 unsigned mask = ~((1 << (regs_written(inst) / reg_width)) - 1) & 0xf; in lower_sampler_logical_send_gen7()
5202 if (reg_width == 2) in lower_sampler_logical_send_gen7()
5203 mlen = length * reg_width - header_size; in lower_sampler_logical_send_gen7()
5205 mlen = length * reg_width; in lower_sampler_logical_send_gen7()
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| D | brw_fs_generator.cpp | 78 const unsigned reg_width = REG_SIZE / (reg->stride * type_sz(reg->type)); in brw_reg_from_fs_reg() local
102 const unsigned width = MIN3(reg_width, phys_width, max_hw_width); in brw_reg_from_fs_reg()
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| /external/arm-trusted-firmware/services/spd/trusty/ |
| D | trusty.c | 311 uint64_t reg_width = GET_RW(read_ctx_reg(get_el3state_ctx(&ctx->cpu_ctx), in trusty_init() local
331 if ((cpu != 0U) && (reg_width == MODE_RW_32)) { in trusty_init()
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| /external/mesa3d/src/freedreno/registers/ |
| D | rules-ng-ng.txt | 148 reg_width / domain_width cells in the domain. It's an error to define a
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| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 2833 int64_t ExtendValue(unsigned reg_width,
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