| /external/mesa3d/src/amd/compiler/ |
| D | aco_instruction_selection_setup.cpp | 659 RegClass *regclasses = ctx->program->temp_rc.data() + ctx->first_temp_id; in init_context() local
746 if (regclasses[alu_instr->src[i].src.ssa->index].type() == RegType::vgpr) in init_context()
753 regclasses[alu_instr->dest.dest.ssa.index] = rc; in init_context()
760 regclasses[nir_instr_as_load_const(instr)->def.index] = rc; in init_context()
880 if (regclasses[intrinsic->src[i].ssa->index].type() == RegType::vgpr) in init_context()
886 regclasses[intrinsic->dest.ssa.index] = rc; in init_context()
936 regclasses[tex->dest.ssa.index] = rc; in init_context()
941 regclasses[entry->dest.ssa.index] = regclasses[entry->src.ssa->index]; in init_context()
949 regclasses[nir_instr_as_ssa_undef(instr)->def.index] = rc; in init_context()
961 regclasses[phi->dest.ssa.index] = RegClass(type, size); in init_context()
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 63 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue()
364 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta()
368 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta()
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| D | ScheduleDAGRRList.cpp | 1767 for (const TargetRegisterClass *RC : TRI->regclasses()) in RegReductionPQBase()
2076 for (const TargetRegisterClass *RC : TRI->regclasses()) { in dumpRegPressure()
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| D | TargetLowering.cpp | 4492 for (const TargetRegisterClass *RC : RI->regclasses()) { in getRegForInlineAsmConstraint()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 59 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue()
360 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta()
364 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta()
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| D | ScheduleDAGRRList.cpp | 1767 for (const TargetRegisterClass *RC : TRI->regclasses()) in RegReductionPQBase()
2073 for (const TargetRegisterClass *RC : TRI->regclasses()) { in dumpRegPressure()
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| D | TargetLowering.cpp | 4197 for (const TargetRegisterClass *RC : RI->regclasses()) { in getRegForInlineAsmConstraint()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 172 for (const TargetRegisterClass *C : TRI->regclasses()) { in computePSetLimit()
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| D | TargetRegisterInfo.cpp | 197 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass()
226 for (const TargetRegisterClass *C : regclasses()) in getAllocatableSet()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 172 for (const TargetRegisterClass *C : TRI->regclasses()) { in computePSetLimit()
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| D | TargetRegisterInfo.cpp | 217 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass()
246 for (const TargetRegisterClass *C : regclasses()) in getAllocatableSet()
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| D | RDFRegisters.cpp | 33 for (const TargetRegisterClass *RC : TRI.regclasses()) { in PhysicalRegisterInfo()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | RDFRegisters.cpp | 33 for (const TargetRegisterClass *RC : TRI.regclasses()) { in PhysicalRegisterInfo()
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| D | HexagonBlockRanges.cpp | 224 for (const TargetRegisterClass *RC : TRI.regclasses()) { in HexagonBlockRanges()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 661 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
|
| /external/llvm-project/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 526 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 526 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 680 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonBlockRanges.cpp | 224 for (const TargetRegisterClass *RC : TRI.regclasses()) { in HexagonBlockRanges()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedFalkorDetails.td | 581 // FIXME: This could be better modeled by looking at the regclasses of the operands.
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedFalkorDetails.td | 581 // FIXME: This could be better modeled by looking at the regclasses of the operands.
|
| /external/mesa3d/docs/relnotes/ |
| D | 20.1.0.rst | 1196 - aco: add sub-dword regclasses
1240 - aco: setup subdword regclasses for ssa_undef & load_const
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| D | 20.3.0.rst | 4042 - aco: keep track of temporaries' regclasses in the Program
|