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Searched refs:res14 (Results 1 – 25 of 26) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c332 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vpx_iadst16_1d_columns_addblk_msa() local
480 ILVR_B2_SH(zero, dst14, zero, dst15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
481 ADD2(res14, out14, res15, out15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
482 CLIP_SH2_0_255(res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
483 PCKEV_B2_SH(res14, res14, res15, res15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
484 ST8x1_UB(res14, dst + 5 * dst_stride); in vpx_iadst16_1d_columns_addblk_msa()
/external/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
Dlogical.ll18 %res14 = and <8 x i32> undef, undef
39 ; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res14 = and <8 x i32> undef, …
64 %res14 = ashr <8 x i32> undef, undef
85 ; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res14 = ashr <8 x i32> undef,…
110 %res14 = lshr <8 x i32> undef, undef
131 ; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res14 = lshr <8 x i32> undef,…
156 %res14 = or <8 x i32> undef, undef
177 ; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res14 = or <8 x i32> undef, u…
202 %res14 = shl <8 x i32> undef, undef
223 ; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res14 = shl <8 x i32> undef, …
[all …]
Dint-arith.ll21 %res14 = add <8 x i32> undef, undef
42 ; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res14 = add <8 x i32> undef, …
67 %res14 = sub <8 x i32> undef, undef
88 ; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res14 = sub <8 x i32> undef, …
113 %res14 = mul <8 x i32> undef, undef
134 ; CHECK: Cost Model: Found an estimated cost of 2 for instruction: %res14 = mul <8 x i32> undef, …
/external/llvm/test/Bitcode/
DmemInstructions.3.2.ll69 ; CHECK-NEXT: %res14 = load volatile i8, i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!in…
70 %res14 = load volatile i8, i8* %ptr1, !nontemporal !0, !invariant.load !1
125 ; CHECK-NEXT: %res14 = load atomic volatile i8, i8* %ptr1 singlethread monotonic, align 1
126 %res14 = load atomic volatile i8, i8* %ptr1 singlethread monotonic, align 1
283 ; CHECK-NEXT: %res14 = extractvalue { i32, i1 } [[TMP]], 0
284 %res14 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
DmiscInstructions.3.2.ll156 ; CHECK-NEXT: %res14 = fcmp uno float %x1, %x2
157 %res14 = fcmp uno float %x1, %x2
/external/llvm-project/llvm/test/Bitcode/
DmemInstructions.3.2.ll69 ; CHECK-NEXT: %res14 = load volatile i8, i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!in…
70 %res14 = load volatile i8, i8* %ptr1, !nontemporal !0, !invariant.load !1
125 ; CHECK-NEXT: %res14 = load atomic volatile i8, i8* %ptr1 syncscope("singlethread") monotonic, alig…
126 %res14 = load atomic volatile i8, i8* %ptr1 syncscope("singlethread") monotonic, align 1
283 ; CHECK-NEXT: %res14 = extractvalue { i32, i1 } [[TMP]], 0
284 %res14 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
DmiscInstructions.3.2.ll156 ; CHECK-NEXT: %res14 = fcmp uno float %x1, %x2
157 %res14 = fcmp uno float %x1, %x2
/external/swiftshader/third_party/subzero/crosstest/
Dtest_vector_ops_ll.ll181 %res14 = zext <16 x i1> %res14_i1 to <16 x i8>
182 ret <16 x i8> %res14
333 %res14 = insertelement <16 x i8> %vec, i8 %elt, i32 14
334 ret <16 x i8> %res14
525 %res14 = zext i1 %res14_i1 to i64
526 ret i64 %res14
701 %res14 = zext i8 %res14_i8 to i64
702 ret i64 %res14
/external/clang/test/SemaOpenCL/
Dvec_step.cl30 …int res14 = vec_step(int16*); // expected-error {{'vec_step' requires built-in scalar or vector ty…
/external/llvm-project/clang/test/SemaOpenCL/
Dvec_step.cl30 …int res14 = vec_step(int16*); // expected-error {{'vec_step' requires built-in scalar or vector ty…
/external/eigen/test/
Devaluators.cpp186 Matrix<float, 1, 4> m14, res14; m14.setRandom(1,4); in test_evaluators() local
198 VERIFY_IS_APPROX_EVALUATOR2(res14, prod(m11,m14), m11*m14); in test_evaluators()
199 VERIFY_IS_APPROX_EVALUATOR2(res14, prod(m14,m44), m14*m44); in test_evaluators()
200 VERIFY_IS_APPROX_EVALUATOR2(res14, prod(m1X,mX4), m1X*mX4); in test_evaluators()
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dint-uadd-10.ll258 %res14 = or i1 %res13, %obit14
262 %res15 = or i1 %res14, %obit15
390 %res14 = or i1 %res13, %obit14
394 %res15 = or i1 %res14, %obit15
Dint-ssub-08.ll268 %res14 = or i1 %res13, %obit14
272 %res15 = or i1 %res14, %obit15
400 %res14 = or i1 %res13, %obit14
404 %res15 = or i1 %res14, %obit15
Dint-sadd-09.ll268 %res14 = or i1 %res13, %obit14
272 %res15 = or i1 %res14, %obit15
400 %res14 = or i1 %res13, %obit14
404 %res15 = or i1 %res14, %obit15
Dint-usub-10.ll268 %res14 = or i1 %res13, %obit14
272 %res15 = or i1 %res14, %obit15
400 %res14 = or i1 %res13, %obit14
404 %res15 = or i1 %res14, %obit15
Dint-sadd-08.ll268 %res14 = or i1 %res13, %obit14
272 %res15 = or i1 %res14, %obit15
400 %res14 = or i1 %res13, %obit14
404 %res15 = or i1 %res14, %obit15
Dint-ssub-09.ll268 %res14 = or i1 %res13, %obit14
272 %res15 = or i1 %res14, %obit15
400 %res14 = or i1 %res13, %obit14
404 %res15 = or i1 %res14, %obit15
Dint-usub-11.ll269 %res14 = or i1 %res13, %obit14
273 %res15 = or i1 %res14, %obit15
Dint-uadd-11.ll259 %res14 = or i1 %res13, %obit14
263 %res15 = or i1 %res14, %obit15
/external/libvpx/libvpx/vpx_dsp/x86/
Dfwd_txfm_impl_sse2.h621 __m128i res08, res09, res10, res11, res12, res13, res14, res15; in FDCT16x16_2D() local
848 res14 = mult_round_shift(&t0, &t1, &k__cospi_m04_p28, in FDCT16x16_2D()
856 check_epi16_overflow_x4(&res02, &res14, &res10, &res06); in FDCT16x16_2D()
1002 &res14, &res15, pass, out0 + 8, out1 + 8); in FDCT16x16_2D()
/external/llvm-project/llvm/test/CodeGen/X86/
Dmerge-consecutive-loads-512.ll558 %res14 = insertelement <64 x i8> %res7, i8 0, i8 14
559 %res15 = insertelement <64 x i8> %res14, i8 0, i8 15
586 %res14 = insertelement <64 x i8> %res3, i8 0, i8 14
587 %res15 = insertelement <64 x i8> %res14, i8 0, i8 15
Davx-intrinsics-fast-isel.ll1558 %res14 = insertelement <32 x i8> %res13, i8 %a17, i32 14
1559 %res15 = insertelement <32 x i8> %res14, i8 %a16, i32 15
1662 %res14 = insertelement <16 x i16> %res13, i16 %a1 , i32 14
1663 %res15 = insertelement <16 x i16> %res14, i16 %a0 , i32 15
1871 %res14 = insertelement <32 x i8> %res13, i8 %a0, i32 14
1872 %res15 = insertelement <32 x i8> %res14, i8 %a0, i32 15
1924 %res14 = insertelement <16 x i16> %res13, i16 %a0, i32 14
1925 %res15 = insertelement <16 x i16> %res14, i16 %a0, i32 15
2174 %res14 = insertelement <32 x i8> %res13, i8 %a14, i32 14
2175 %res15 = insertelement <32 x i8> %res14, i8 %a15, i32 15
[all …]
/external/llvm/test/CodeGen/X86/
Dmerge-consecutive-loads-512.ll603 %res14 = insertelement <64 x i8> %res7, i8 0, i8 14
604 %res15 = insertelement <64 x i8> %res14, i8 0, i8 15
638 %res14 = insertelement <64 x i8> %res3, i8 0, i8 14
639 %res15 = insertelement <64 x i8> %res14, i8 0, i8 15
Davx-intrinsics-fast-isel.ll2010 %res14 = insertelement <32 x i8> %res13, i8 %a17, i32 14
2011 %res15 = insertelement <32 x i8> %res14, i8 %a16, i32 15
2114 %res14 = insertelement <16 x i16> %res13, i16 %a1 , i32 14
2115 %res15 = insertelement <16 x i16> %res14, i16 %a0 , i32 15
2341 %res14 = insertelement <32 x i8> %res13, i8 %a0, i32 14
2342 %res15 = insertelement <32 x i8> %res14, i8 %a0, i32 15
2394 %res14 = insertelement <16 x i16> %res13, i16 %a0, i32 14
2395 %res15 = insertelement <16 x i16> %res14, i16 %a0, i32 15
2647 %res14 = insertelement <32 x i8> %res13, i8 %a14, i32 14
2648 %res15 = insertelement <32 x i8> %res14, i8 %a15, i32 15
[all …]
Dsse2-intrinsics-fast-isel.ll2155 %res14 = insertelement <16 x i8> %res13, i8 %a1 , i32 14
2156 %res15 = insertelement <16 x i8> %res14, i8 %a0 , i32 15
2342 %res14 = insertelement <16 x i8> %res13, i8 %a0, i32 14
2343 %res15 = insertelement <16 x i8> %res14, i8 %a0, i32 15
2549 %res14 = insertelement <16 x i8> %res13, i8 %a14, i32 14
2550 %res15 = insertelement <16 x i8> %res14, i8 %a15, i32 15

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