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Searched refs:res15 (Results 1 – 25 of 25) sorted by relevance

/external/libvpx/libvpx/vpx_dsp/mips/
Didct16x16_msa.c332 v8i16 res8, res9, res10, res11, res12, res13, res14, res15; in vpx_iadst16_1d_columns_addblk_msa() local
480 ILVR_B2_SH(zero, dst14, zero, dst15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
481 ADD2(res14, out14, res15, out15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
482 CLIP_SH2_0_255(res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
483 PCKEV_B2_SH(res14, res14, res15, res15, res14, res15); in vpx_iadst16_1d_columns_addblk_msa()
485 ST8x1_UB(res15, dst + 10 * dst_stride); in vpx_iadst16_1d_columns_addblk_msa()
/external/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
Dlogical.ll19 %res15 = and <8 x i64> undef, undef
40 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = and <8 x i64> undef, …
65 %res15 = ashr <8 x i64> undef, undef
86 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = ashr <8 x i64> undef,…
111 %res15 = lshr <8 x i64> undef, undef
132 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = lshr <8 x i64> undef,…
157 %res15 = or <8 x i64> undef, undef
178 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = or <8 x i64> undef, u…
203 %res15 = shl <8 x i64> undef, undef
224 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = shl <8 x i64> undef, …
[all …]
Dint-arith.ll22 %res15 = add <8 x i64> undef, undef
43 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = add <8 x i64> undef, …
68 %res15 = sub <8 x i64> undef, undef
89 ; CHECK: Cost Model: Found an estimated cost of 4 for instruction: %res15 = sub <8 x i64> undef, …
114 %res15 = mul <8 x i64> undef, undef
135 ; CHECK: Cost Model: Found an estimated cost of 12 for instruction: %res15 = mul <8 x i64> undef,…
/external/llvm/test/Bitcode/
DmemInstructions.3.2.ll72 ; CHECK-NEXT: %res15 = load i8, i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!in…
73 %res15 = load i8, i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
128 ; CHECK-NEXT: %res15 = load atomic volatile i8, i8* %ptr1 singlethread acquire, align 1
129 %res15 = load atomic volatile i8, i8* %ptr1 singlethread acquire, align 1
287 ; CHECK-NEXT: %res15 = extractvalue { i32, i1 } [[TMP]], 0
288 %res15 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
DmiscInstructions.3.2.ll159 ; CHECK-NEXT: %res15 = fcmp true float %x1, %x2
160 %res15 = fcmp true float %x1, %x2
/external/llvm-project/llvm/test/Bitcode/
DmemInstructions.3.2.ll72 ; CHECK-NEXT: %res15 = load i8, i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!in…
73 %res15 = load i8, i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
128 ; CHECK-NEXT: %res15 = load atomic volatile i8, i8* %ptr1 syncscope("singlethread") acquire, align 1
129 %res15 = load atomic volatile i8, i8* %ptr1 syncscope("singlethread") acquire, align 1
287 ; CHECK-NEXT: %res15 = extractvalue { i32, i1 } [[TMP]], 0
288 %res15 = cmpxchg i32* %ptr, i32 %cmp, i32 %new syncscope("singlethread") acq_rel acquire
DmiscInstructions.3.2.ll159 ; CHECK-NEXT: %res15 = fcmp true float %x1, %x2
160 %res15 = fcmp true float %x1, %x2
/external/swiftshader/third_party/subzero/crosstest/
Dtest_vector_ops_ll.ll185 %res15 = zext <16 x i1> %res15_i1 to <16 x i8>
186 ret <16 x i8> %res15
336 %res15 = insertelement <16 x i8> %vec, i8 %elt, i32 15
337 ret <16 x i8> %res15
529 %res15 = zext i1 %res15_i1 to i64
530 ret i64 %res15
705 %res15 = zext i8 %res15_i8 to i64
706 ret i64 %res15
/external/clang/test/SemaOpenCL/
Dvec_step.cl31 …int res15 = vec_step(void(void)); // expected-error {{'vec_step' requires built-in scalar or vecto…
/external/llvm-project/clang/test/SemaOpenCL/
Dvec_step.cl31 …int res15 = vec_step(void(void)); // expected-error {{'vec_step' requires built-in scalar or vecto…
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dint-uadd-10.ll262 %res15 = or i1 %res14, %obit15
283 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
394 %res15 = or i1 %res14, %obit15
415 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
Dint-ssub-08.ll272 %res15 = or i1 %res14, %obit15
293 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
404 %res15 = or i1 %res14, %obit15
425 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
Dint-sadd-09.ll272 %res15 = or i1 %res14, %obit15
293 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
404 %res15 = or i1 %res14, %obit15
425 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
Dint-usub-10.ll272 %res15 = or i1 %res14, %obit15
293 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
404 %res15 = or i1 %res14, %obit15
425 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
Dint-sadd-08.ll272 %res15 = or i1 %res14, %obit15
293 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
404 %res15 = or i1 %res14, %obit15
425 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
Dint-ssub-09.ll272 %res15 = or i1 %res14, %obit15
293 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
404 %res15 = or i1 %res14, %obit15
425 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
Dint-usub-11.ll273 %res15 = or i1 %res14, %obit15
294 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
Dint-uadd-11.ll263 %res15 = or i1 %res14, %obit15
284 %res = phi i1 [ 0, %entry ], [ %res15, %add ]
/external/libvpx/libvpx/vpx_dsp/x86/
Dfwd_txfm_impl_sse2.h621 __m128i res08, res09, res10, res11, res12, res13, res14, res15; in FDCT16x16_2D() local
964 res15 = mult_round_shift(&t0, &t1, &k__cospi_m02_p30, in FDCT16x16_2D()
969 overflow = check_epi16_overflow_x4(&res01, &res09, &res15, &res07); in FDCT16x16_2D()
1002 &res14, &res15, pass, out0 + 8, out1 + 8); in FDCT16x16_2D()
/external/llvm-project/llvm/test/CodeGen/X86/
Dmerge-consecutive-loads-512.ll559 %res15 = insertelement <64 x i8> %res14, i8 0, i8 15
560 %res16 = insertelement <64 x i8> %res15, i8 0, i8 16
587 %res15 = insertelement <64 x i8> %res14, i8 0, i8 15
588 %res16 = insertelement <64 x i8> %res15, i8 0, i8 16
Davx-intrinsics-fast-isel.ll1559 %res15 = insertelement <32 x i8> %res14, i8 %a16, i32 15
1560 %res16 = insertelement <32 x i8> %res15, i8 %a15, i32 16
1663 %res15 = insertelement <16 x i16> %res14, i16 %a0 , i32 15
1664 %res = bitcast <16 x i16> %res15 to <4 x i64>
1872 %res15 = insertelement <32 x i8> %res14, i8 %a0, i32 15
1873 %res16 = insertelement <32 x i8> %res15, i8 %a0, i32 16
1925 %res15 = insertelement <16 x i16> %res14, i16 %a0, i32 15
1926 %res = bitcast <16 x i16> %res15 to <4 x i64>
2175 %res15 = insertelement <32 x i8> %res14, i8 %a15, i32 15
2176 %res16 = insertelement <32 x i8> %res15, i8 %a16, i32 16
[all …]
Dsse2-intrinsics-fast-isel.ll3318 %res15 = insertelement <16 x i8> %res14, i8 %a0 , i32 15
3319 %res = bitcast <16 x i8> %res15 to <2 x i64>
3820 %res15 = insertelement <16 x i8> %res14, i8 %a0, i32 15
3821 %res = bitcast <16 x i8> %res15 to <2 x i64>
4328 %res15 = insertelement <16 x i8> %res14, i8 %a15, i32 15
4329 %res = bitcast <16 x i8> %res15 to <2 x i64>
/external/llvm/test/CodeGen/X86/
Dmerge-consecutive-loads-512.ll604 %res15 = insertelement <64 x i8> %res14, i8 0, i8 15
605 %res16 = insertelement <64 x i8> %res15, i8 0, i8 16
639 %res15 = insertelement <64 x i8> %res14, i8 0, i8 15
640 %res16 = insertelement <64 x i8> %res15, i8 0, i8 16
Davx-intrinsics-fast-isel.ll2011 %res15 = insertelement <32 x i8> %res14, i8 %a16, i32 15
2012 %res16 = insertelement <32 x i8> %res15, i8 %a15, i32 16
2115 %res15 = insertelement <16 x i16> %res14, i16 %a0 , i32 15
2116 %res = bitcast <16 x i16> %res15 to <4 x i64>
2342 %res15 = insertelement <32 x i8> %res14, i8 %a0, i32 15
2343 %res16 = insertelement <32 x i8> %res15, i8 %a0, i32 16
2395 %res15 = insertelement <16 x i16> %res14, i16 %a0, i32 15
2396 %res = bitcast <16 x i16> %res15 to <4 x i64>
2648 %res15 = insertelement <32 x i8> %res14, i8 %a15, i32 15
2649 %res16 = insertelement <32 x i8> %res15, i8 %a16, i32 16
[all …]
Dsse2-intrinsics-fast-isel.ll2156 %res15 = insertelement <16 x i8> %res14, i8 %a0 , i32 15
2157 %res = bitcast <16 x i8> %res15 to <2 x i64>
2343 %res15 = insertelement <16 x i8> %res14, i8 %a0, i32 15
2344 %res = bitcast <16 x i8> %res15 to <2 x i64>
2550 %res15 = insertelement <16 x i8> %res14, i8 %a15, i32 15
2551 %res = bitcast <16 x i8> %res15 to <2 x i64>