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Searched refs:s_ashr_i32 (Results 1 – 25 of 53) sorted by relevance

123

/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dashr.ll61 ; GFX6-NEXT: s_ashr_i32 s0, s0, s1
68 ; GFX8-NEXT: s_ashr_i32 s0, s0, s1
75 ; GFX9-NEXT: s_ashr_i32 s0, s0, s1
85 ; GCN-NEXT: s_ashr_i32 s0, s0, 7
120 ; GCN-NEXT: s_ashr_i32 s0, s0, s1
130 ; GCN-NEXT: s_ashr_i32 s0, s0, 7
156 define amdgpu_ps i32 @s_ashr_i32(i32 inreg %value, i32 inreg %amount) {
157 ; GCN-LABEL: s_ashr_i32:
159 ; GCN-NEXT: s_ashr_i32 s0, s0, s1
168 ; GCN-NEXT: s_ashr_i32 s0, s0, 31
[all …]
Dcombine-shift-of-shifted-logic.ll81 ; CHECK-NEXT: s_ashr_i32 s0, s0, 4
94 ; CHECK-NEXT: s_ashr_i32 s0, s0, 8
107 ; CHECK-NEXT: s_ashr_i32 s0, s0, 5
196 ; CHECK-NEXT: s_ashr_i32 s0, s0, 4
208 ; CHECK-NEXT: s_ashr_i32 s0, s0, 8
221 ; CHECK-NEXT: s_ashr_i32 s0, s0, 5
310 ; CHECK-NEXT: s_ashr_i32 s0, s0, 4
323 ; CHECK-NEXT: s_ashr_i32 s0, s0, 6
335 ; CHECK-NEXT: s_ashr_i32 s0, s0, 5
Dcombine-shift-imm-chain.ll61 ; CHECK-NEXT: s_ashr_i32 s0, s0, 5
72 ; CHECK-NEXT: s_ashr_i32 s0, s0, 10
85 ; CHECK-NEXT: s_ashr_i32 s0, s0, 31
98 ; CHECK-NEXT: s_ashr_i32 s0, s1, 31
Dssubsat.ll76 ; GFX6-NEXT: s_ashr_i32 s0, s0, 25
102 ; GFX8-NEXT: s_ashr_i32 s0, s0, s2
198 ; GFX6-NEXT: s_ashr_i32 s0, s0, 24
224 ; GFX8-NEXT: s_ashr_i32 s0, s0, s2
380 ; GFX6-NEXT: s_ashr_i32 s0, s0, 24
394 ; GFX6-NEXT: s_ashr_i32 s1, s1, 24
430 ; GFX8-NEXT: s_ashr_i32 s0, s0, s4
449 ; GFX8-NEXT: s_ashr_i32 s1, s1, s4
736 ; GFX6-NEXT: s_ashr_i32 s0, s0, 24
750 ; GFX6-NEXT: s_ashr_i32 s1, s1, 24
[all …]
Dsaddsat.ll76 ; GFX6-NEXT: s_ashr_i32 s0, s0, 25
102 ; GFX8-NEXT: s_ashr_i32 s0, s0, s2
198 ; GFX6-NEXT: s_ashr_i32 s0, s0, 24
224 ; GFX8-NEXT: s_ashr_i32 s0, s0, s2
380 ; GFX6-NEXT: s_ashr_i32 s0, s0, 24
394 ; GFX6-NEXT: s_ashr_i32 s1, s1, 24
430 ; GFX8-NEXT: s_ashr_i32 s0, s0, s4
449 ; GFX8-NEXT: s_ashr_i32 s1, s1, s4
736 ; GFX6-NEXT: s_ashr_i32 s0, s0, 24
750 ; GFX6-NEXT: s_ashr_i32 s1, s1, 24
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dload-constant-i32.ll93 ; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[SLO]], 31
120 ; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[LO]], 31
142 ; GCN-DAG: s_ashr_i32
143 ; GCN-DAG: s_ashr_i32
168 ; GCN: s_ashr_i32
169 ; GCN: s_ashr_i32
170 ; GCN: s_ashr_i32
171 ; GCN: s_ashr_i32
204 ; GCN: s_ashr_i32
205 ; GCN: s_ashr_i32
[all …]
Dsign_extend.ll15 ; GCN: s_ashr_i32
39 ; GCN: s_ashr_i32
70 ; GCN-DAG: s_ashr_i32 [[EXT3:s[0-9]+]], [[VAL]], 24
126 ; GCN-DAG: s_ashr_i32 s{{[0-9]+}}, s{{[0-9]+}}, 16
Dload-constant-i16.ll140 ; GCN-DAG: s_ashr_i32
194 ; GCN-DAG: s_ashr_i32
229 ; GCN-DAG: s_ashr_i32
251 ; GCN-DAG: s_ashr_i32
274 ; GCN-DAG: s_ashr_i32
Dsra.ll205 ; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31
232 ; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dload-constant-i32.ll95 ; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[SLO]], 31
122 ; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[LO]], 31
144 ; GCN-DAG: s_ashr_i32
145 ; GCN-DAG: s_ashr_i32
170 ; GCN: s_ashr_i32
171 ; GCN: s_ashr_i32
172 ; GCN: s_ashr_i32
173 ; GCN: s_ashr_i32
206 ; GCN: s_ashr_i32
207 ; GCN: s_ashr_i32
[all …]
Didot4s.ll33 ; GFX7-NEXT: s_ashr_i32 s5, s5, 24
35 ; GFX7-NEXT: s_ashr_i32 s4, s4, 24
62 ; GFX8-NEXT: s_ashr_i32 s3, s3, 24
64 ; GFX8-NEXT: s_ashr_i32 s2, s2, 24
94 ; GFX9-NODL-NEXT: s_ashr_i32 s3, s3, 24
96 ; GFX9-NODL-NEXT: s_ashr_i32 s2, s2, 24
197 ; GFX7-NEXT: s_ashr_i32 s5, s5, 24
201 ; GFX7-NEXT: s_ashr_i32 s4, s4, 24
234 ; GFX8-NEXT: s_ashr_i32 s1, s1, 24
236 ; GFX8-NEXT: s_ashr_i32 s0, s0, 24
[all …]
Dload-constant-i16.ll963 ; GCN-NOHSA-SI-NEXT: s_ashr_i32 s4, s2, 16
979 ; GCN-HSA-NEXT: s_ashr_i32 s0, s2, 16
996 ; GCN-NOHSA-VI-NEXT: s_ashr_i32 s0, s2, 16
1125 ; GCN-NOHSA-SI-NEXT: s_ashr_i32 s6, s4, 16
1144 ; GCN-HSA-NEXT: s_ashr_i32 s2, s0, 16
1163 ; GCN-NOHSA-VI-NEXT: s_ashr_i32 s6, s4, 16
1312 ; GCN-NOHSA-SI-NEXT: s_ashr_i32 s8, s4, 16
1333 ; GCN-HSA-NEXT: s_ashr_i32 s4, s0, 16
1353 ; GCN-NOHSA-VI-NEXT: s_ashr_i32 s6, s5, 16
1354 ; GCN-NOHSA-VI-NEXT: s_ashr_i32 s7, s4, 16
[all …]
Didot8s.ll55 ; GFX7-NEXT: s_ashr_i32 s5, s5, 28
57 ; GFX7-NEXT: s_ashr_i32 s4, s4, 28
108 ; GFX8-NEXT: s_ashr_i32 s3, s3, 28
110 ; GFX8-NEXT: s_ashr_i32 s2, s2, 28
162 ; GFX9-NEXT: s_ashr_i32 s3, s3, 28
164 ; GFX9-NEXT: s_ashr_i32 s2, s2, 28
332 ; GFX7-NEXT: s_ashr_i32 s5, s5, 28
336 ; GFX7-NEXT: s_ashr_i32 s4, s4, 28
395 ; GFX8-NEXT: s_ashr_i32 s1, s1, 28
397 ; GFX8-NEXT: s_ashr_i32 s0, s0, 28
[all …]
Dashr.v2i16.ll15 ; CIVI-DAG: s_ashr_i32
16 ; CIVI-DAG: s_ashr_i32
19 ; CIVI-DAG: s_ashr_i32
20 ; CIVI-DAG: s_ashr_i32
Didot2.ll298 ; GFX7-NEXT: s_ashr_i32 s4, s4, 16
300 ; GFX7-NEXT: s_ashr_i32 s5, s5, 16
319 ; GFX8-NEXT: s_ashr_i32 s2, s2, 16
321 ; GFX8-NEXT: s_ashr_i32 s3, s3, 16
343 ; GFX9-NODL-NEXT: s_ashr_i32 s2, s2, 16
345 ; GFX9-NODL-NEXT: s_ashr_i32 s3, s3, 16
688 ; GFX7-NEXT: s_ashr_i32 s4, s4, 16
690 ; GFX7-NEXT: s_ashr_i32 s5, s5, 16
709 ; GFX8-NEXT: s_ashr_i32 s2, s2, 16
711 ; GFX8-NEXT: s_ashr_i32 s3, s3, 16
[all …]
Dsign_extend.ll48 ; SI-NEXT: s_ashr_i32 s0, s1, 31
64 ; VI-NEXT: s_ashr_i32 s0, s1, 31
119 ; SI-NEXT: s_ashr_i32 s1, s0, 31
132 ; VI-NEXT: s_ashr_i32 s1, s0, 31
348 ; SI-NEXT: s_ashr_i32 s1, s0, 24
373 ; VI-NEXT: s_ashr_i32 s1, s0, 24
474 ; SI-NEXT: s_ashr_i32 s5, s6, 16
497 ; VI-NEXT: s_ashr_i32 s5, s6, 16
501 ; VI-NEXT: s_ashr_i32 s4, s7, 16
Dshift-select.ll47 ; GCN-LABEL: name: s_ashr_i32
49 define amdgpu_kernel void @s_ashr_i32(i32 addrspace(1)* %out, i32 %lhs, i32 %rhs) #0 {
Damdgpu-codegenprepare-idiv.ll187 ; GCN-NEXT: s_ashr_i32 s8, s3, 31
192 ; GCN-NEXT: s_ashr_i32 s0, s2, 31
267 ; GCN-NEXT: s_ashr_i32 s4, s3, 31
272 ; GCN-NEXT: s_ashr_i32 s4, s2, 31
432 ; GCN-NEXT: s_ashr_i32 s1, s0, 16
438 ; GCN-NEXT: s_ashr_i32 s0, s0, 30
488 ; GCN-NEXT: s_ashr_i32 s2, s4, 16
494 ; GCN-NEXT: s_ashr_i32 s3, s3, 30
649 ; GCN-NEXT: s_ashr_i32 s0, s0, 30
707 ; GCN-NEXT: s_ashr_i32 s1, s1, 30
[all …]
Dsdiv64.ll14 ; GCN-NEXT: s_ashr_i32 s12, s3, 31
23 ; GCN-NEXT: s_ashr_i32 s14, s11, 31
149 ; GCN-IR-NEXT: s_ashr_i32 s2, s7, 31
151 ; GCN-IR-NEXT: s_ashr_i32 s8, s1, 31
514 ; GCN-NEXT: s_ashr_i32 s4, s4, 30
544 ; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
620 ; GCN-NEXT: s_ashr_i32 s4, s4, 30
648 ; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
686 ; GCN-NEXT: s_ashr_i32 s4, s4, 30
716 ; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30
[all …]
Dbfe-patterns.ll131 ; GCN: s_ashr_i32 s{{[0-9]+}}, [[TMP]], [[SUB]]
146 ; GCN: s_ashr_i32 s{{[0-9]+}}, [[SHL]], [[SUB]]
Dsrem64.ll492 ; GCN-NEXT: s_ashr_i32 s1, s1, 30
524 ; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30
563 ; GCN-NEXT: s_ashr_i32 s1, s1, 30
595 ; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30
688 ; GCN-NEXT: s_ashr_i32 s1, s1, 30
720 ; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30
759 ; GCN-NEXT: s_ashr_i32 s1, s1, 30
791 ; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30
829 ; GCN-NEXT: s_ashr_i32 s1, s1, 30
858 ; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30
[all …]
/external/llvm/test/MC/AMDGPU/
Dsop2.s123 s_ashr_i32 s2, s4, s6 label
/external/llvm-project/llvm/test/MC/AMDGPU/
Dsop2.s166 s_ashr_i32 s2, s4, s6 label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_vi.txt63 # VI: s_ashr_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x90]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dsop2_vi.txt63 # VI: s_ashr_i32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x90]

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