Searched refs:src0_reg (Results 1 – 2 of 2) sorted by relevance
| /external/mesa3d/src/amd/compiler/ |
| D | aco_lower_to_hw_instr.cpp | 199 void emit_int64_dpp_op(lower_context *ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, in emit_int64_dpp_op() argument
207 Operand src0[] = {Operand(src0_reg, v1), Operand(PhysReg{src0_reg+1}, v1)}; in emit_int64_dpp_op()
308 void emit_int64_op(lower_context *ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, PhysReg… in emit_int64_op() argument
312 RegClass src0_rc = src0_reg.reg() >= 256 ? v1 : s1; in emit_int64_op()
313 Operand src0[] = {Operand(src0_reg, src0_rc), Operand(PhysReg{src0_reg+1}, src0_rc)}; in emit_int64_op()
315 Operand src0_64 = Operand(src0_reg, src0_reg.reg() >= 256 ? v2 : s2); in emit_int64_op()
323 src0_reg = vtmp; in emit_int64_op()
374 std::swap(src0_reg, src1_reg); in emit_int64_op()
379 assert(!(src0_reg == src1_reg)); in emit_int64_op()
388 Definition tmp0_def(PhysReg{src0_reg+1}, v1); in emit_int64_op()
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| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_disasm.c | 54 uint32_t src0_reg : 9; member
558 .reg = instr->src0_reg, in print_instr()
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