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/external/llvm-project/llvm/test/CodeGen/NVPTX/
Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
Dintrinsic-old.ll11 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range ![[BLK_IDX_XY:[0-9]+]]
13 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
19 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.y(), !range ![[BLK_IDX_XY]]
21 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
27 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.z(), !range ![[BLK_IDX_Z:[0-9]+]]
29 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
36 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.w()
42 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !range ![[BLK_SIZE_XY:[0-9]+]]
44 %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
50 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.y(), !range ![[BLK_SIZE_XY]]
[all …]
Dintrinsics.ll97 ; Most of nvvm.read.ptx.sreg.* intrinsics always return the same value and may
102 %a = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
104 %b = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
115 %a = tail call i32 @llvm.nvvm.read.ptx.sreg.clock()
117 %b = tail call i32 @llvm.nvvm.read.ptx.sreg.clock()
126 %a = tail call i64 @llvm.nvvm.read.ptx.sreg.clock64()
128 %b = tail call i64 @llvm.nvvm.read.ptx.sreg.clock64()
144 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
145 declare i32 @llvm.nvvm.read.ptx.sreg.clock()
146 declare i64 @llvm.nvvm.read.ptx.sreg.clock64()
/external/llvm/test/CodeGen/NVPTX/
Denvreg.ll4 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
Dintrinsic-old.ll11 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range ![[BLK_IDX_XY:[0-9]+]]
13 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
19 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.y(), !range ![[BLK_IDX_XY]]
21 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
27 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.z(), !range ![[BLK_IDX_Z:[0-9]+]]
29 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
36 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.w()
42 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !range ![[BLK_SIZE_XY:[0-9]+]]
44 %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
50 ; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.y(), !range ![[BLK_SIZE_XY]]
[all …]
/external/llvm-project/mlir/test/Target/
Dnvvmir.mlir4 // CHECK: %1 = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
5 %1 = nvvm.read.ptx.sreg.tid.x : !llvm.i32
6 // CHECK: call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
7 %2 = nvvm.read.ptx.sreg.tid.y : !llvm.i32
8 // CHECK: call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
9 %3 = nvvm.read.ptx.sreg.tid.z : !llvm.i32
10 // CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
11 %4 = nvvm.read.ptx.sreg.ntid.x : !llvm.i32
12 // CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
13 %5 = nvvm.read.ptx.sreg.ntid.y : !llvm.i32
[all …]
/external/llvm-project/mlir/test/Dialect/LLVMIR/
Dnvvm.mlir4 // CHECK: nvvm.read.ptx.sreg.tid.x : !llvm.i32
5 %0 = nvvm.read.ptx.sreg.tid.x : !llvm.i32
6 // CHECK: nvvm.read.ptx.sreg.tid.y : !llvm.i32
7 %1 = nvvm.read.ptx.sreg.tid.y : !llvm.i32
8 // CHECK: nvvm.read.ptx.sreg.tid.z : !llvm.i32
9 %2 = nvvm.read.ptx.sreg.tid.z : !llvm.i32
10 // CHECK: nvvm.read.ptx.sreg.ntid.x : !llvm.i32
11 %3 = nvvm.read.ptx.sreg.ntid.x : !llvm.i32
12 // CHECK: nvvm.read.ptx.sreg.ntid.y : !llvm.i32
13 %4 = nvvm.read.ptx.sreg.ntid.y : !llvm.i32
[all …]
/external/llvm-project/mlir/include/mlir/Dialect/LLVMIR/
DNVVMOps.td61 def NVVM_LaneIdOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.laneid">;
62 def NVVM_WarpSizeOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.warpsize">;
66 def NVVM_ThreadIdXOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.tid.x">;
67 def NVVM_ThreadIdYOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.tid.y">;
68 def NVVM_ThreadIdZOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.tid.z">;
69 def NVVM_BlockDimXOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ntid.x">;
70 def NVVM_BlockDimYOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ntid.y">;
71 def NVVM_BlockDimZOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ntid.z">;
75 def NVVM_BlockIdXOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ctaid.x">;
76 def NVVM_BlockIdYOp : NVVM_SpecialRegisterOp<"read.ptx.sreg.ctaid.y">;
[all …]
/external/llvm-project/llvm/test/CodeGen/AVR/pseudo/
DSBCIWRdK.mir20 ; CHECK: $r20 = SBCIRdK $r20, 175, implicit-def $sreg, implicit killed $sreg
21 ; CHECK-NEXT: $r21 = SBCIRdK $r21, 250, implicit-def $sreg, implicit killed $sreg
23 $r21r20 = SBCIWRdK $r21r20, 64175, implicit-def $sreg, implicit $sreg
DCPCWRdRr.mir20 ; CHECK: CPCRdRr $r20, $r22, implicit-def $sreg, implicit killed $sreg
21 ; CHECK-NEXT: CPCRdRr $r21, $r23, implicit-def $sreg, implicit killed $sreg
23 CPCWRdRr $r21r20, $r23r22, implicit-def $sreg, implicit $sreg
DADCWRdRr.mir20 ; CHECK: $r14 = ADCRdRr $r14, $r20, implicit-def $sreg, implicit $sreg
21 ; CHECK-LABEL: $r15 = ADCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = ADCWRdRr $r15r14, $r21r20, implicit-def $sreg, implicit $sreg
DSBCWRdRr.mir20 ; CHECK: $r14 = SBCRdRr $r14, $r20, implicit-def $sreg
21 ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = SBCWRdRr $r15r14, $r21r20, implicit-def $sreg, implicit $sreg
DASRWRd.mir18 ; CHECK: $r15 = ASRRd $r15, implicit-def $sreg
19 ; CHECK-NEXT: $r14 = RORRd $r14, implicit-def $sreg, implicit killed $sreg
21 $r15r14 = ASRWRd $r15r14, implicit-def $sreg
DLSRWRd.mir18 ; CHECK: $r15 = LSRRd $r15, implicit-def $sreg
19 ; CHECK-NEXT: $r14 = RORRd $r14, implicit-def $sreg, implicit killed $sreg
21 $r15r14 = LSRWRd $r15r14, implicit-def $sreg
DLSLWRd.mir18 ; CHECK: $r14 = ADDRdRr $r14, $r14, implicit-def $sreg
19 ; CHECK-NEXT: $r15 = ADCRdRr $r15, $r15, implicit-def $sreg, implicit killed $sreg
21 $r15r14 = LSLWRd $r15r14, implicit-def $sreg
DADDWRdRr.mir20 ; CHECK: $r14 = ADDRdRr $r14, $r20, implicit-def $sreg
21 ; CHECK-LABEL: $r15 = ADCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = ADDWRdRr $r15r14, $r21r20, implicit-def $sreg
DCPWRdRr.mir20 ; CHECK: CPRdRr $r14, $r20, implicit-def $sreg
21 ; CHECK-NEXT: CPCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
23 CPWRdRr $r15r14, $r21r20, implicit-def $sreg
DSUBWRdRr.mir20 ; CHECK: $r14 = SUBRdRr $r14, $r20, implicit-def $sreg
21 ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = SUBWRdRr $r15r14, $r21r20, implicit-def $sreg
DSUBIWRdK.mir20 ; CHECK: $r20 = SUBIRdK $r20, 175, implicit-def $sreg
21 ; CHECK-NEXT: $r21 = SBCIRdK $r21, 250, implicit-def $sreg, implicit killed $sreg
23 $r21r20 = SUBIWRdK $r21r20, 64175, implicit-def $sreg
DNEGWRd.mir20 ; CHECK: $r15 = NEGRd $r15, implicit-def dead $sreg
22 ; CHECK-NEXT: $r15 = SBCIRdK $r15, 0, implicit-def $sreg, implicit killed $sreg
24 $r15r14 = NEGWRd $r15r14, implicit-def $sreg
DSEXT.mir20 ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg
21 ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = SEXT $r31, implicit-def $sreg
DZEXT.mir20 ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg
21 ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = SEXT $r31, implicit-def $sreg
/external/llvm-project/llvm/test/Analysis/DivergenceAnalysis/NVPTX/
Ddaorder.ll9 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
41 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
42 declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
43 declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
44 declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
Dirreducible.ll22 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
49 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
50 declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
51 declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
52 declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
Ddiverge.ll10 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
32 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
53 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
103 %laneid = call i32 @llvm.nvvm.read.ptx.sreg.laneid()
125 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
149 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
165 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
166 declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
167 declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
168 declare i32 @llvm.nvvm.read.ptx.sreg.laneid()

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