| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | armv8.4a-ldst-error.s | 44 stlur w20, [x27, #256] label
56 stlur x10, [x2, #256] label
|
| D | armv8.4a-ldst.s | 98 stlur w20, [x27, #255] label
128 stlur x10, [x2, #255] label
|
| /external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.4a-ldst.txt | 101 #CHECK-NEXT: stlur w19, [x26]
102 #CHECK-NEXT: stlur w19, [x26, #-256]
103 #CHECK-NEXT: stlur w20, [x27, #255]
104 #CHECK-NEXT: stlur w21, [sp, #5]
113 #CHECK-NEXT: stlur x9, [x1]
114 #CHECK-NEXT: stlur x9, [x1, #-256]
115 #CHECK-NEXT: stlur x10, [x2, #255]
116 #CHECK-NEXT: stlur x11, [sp, #8]
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 1848 COMPARE(stlur(w28, MemOperand(x29)), "stlur w28, [x29]"); in TEST()
1849 COMPARE(stlur(w0, MemOperand(sp, 64)), "stlur w0, [sp, #64]"); in TEST()
1850 COMPARE(stlur(x1, MemOperand(x2)), "stlur x1, [x2]"); in TEST()
1851 COMPARE(stlur(x3, MemOperand(sp, 64)), "stlur x3, [sp, #64]"); in TEST()
|
| D | test-cpu-features-aarch64.cc | 3557 TEST_RCPC_RCPCIMM(stlur_0, stlur(w0, MemOperand(x1, 40)))
3558 TEST_RCPC_RCPCIMM(stlur_1, stlur(x0, MemOperand(x1, 209)))
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 1470 void stlur(const Register& rt, const MemOperand& dst);
|
| D | assembler-aarch64.cc | 1568 void Assembler::stlur(const Register& rt, const MemOperand& dst) { in stlur() function in vixl::aarch64::Assembler
|
| D | macro-assembler-aarch64.h | 2368 stlur(rt, dst); in Stlr()
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2558 void stlur(const Register& rt, const MemOperand& dst)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3002 defm STLURW : BaseStoreUnscaleV84<"stlur", 0b10, 0b00, GPR32>;
3003 defm STLURX : BaseStoreUnscaleV84<"stlur", 0b11, 0b00, GPR64>;
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 3202 defm STLURW : BaseStoreUnscaleV84<"stlur", 0b10, 0b00, GPR32>;
3203 defm STLURX : BaseStoreUnscaleV84<"stlur", 0b11, 0b00, GPR64>;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 12586 "stllrb\006stllrh\004stlr\005stlrb\005stlrh\005stlur\006stlurb\006stlurh"
18752 …{ 5515 /* stlur */, AArch64::STLURWi, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasRCPC_IMMO, { MCK…
18753 …{ 5515 /* stlur */, AArch64::STLURXi, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasRCPC_IMMO, { MCK…
18754 …{ 5515 /* stlur */, AArch64::STLURWi, Convert__Reg1_0__Reg1_2__SImm91_3, AMFBS_HasRCPC_IMMO, { MCK…
18755 …{ 5515 /* stlur */, AArch64::STLURXi, Convert__Reg1_0__Reg1_2__SImm91_3, AMFBS_HasRCPC_IMMO, { MCK…
26125 …{ 5515 /* stlur */, AArch64::STLURWi, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasRCPC_IMMO, { MCK…
26126 …{ 5515 /* stlur */, AArch64::STLURXi, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasRCPC_IMMO, { MCK…
26127 …{ 5515 /* stlur */, AArch64::STLURWi, Convert__Reg1_0__Reg1_2__SImm91_3, AMFBS_HasRCPC_IMMO, { MCK…
26128 …{ 5515 /* stlur */, AArch64::STLURXi, Convert__Reg1_0__Reg1_2__SImm91_3, AMFBS_HasRCPC_IMMO, { MCK…
|
| D | AArch64GenAsmWriter.inc | 22763 /* 12566 */ "stlur $\x01, [$\x02]\0"
|
| D | AArch64GenAsmWriter1.inc | 23484 /* 12544 */ "stlur $\x01, [$\x02]\0"
|