Searched refs:sxtw (Results 1 – 25 of 245) sorted by relevance
12345678910
41 sxtw x2, w243 sxtw x3, w345 sxtw x4, w447 sxtw x5, w554 sxtw x2, w256 sxtw x3, w358 sxtw x4, w460 sxtw x5, w586 sxtw x2, w288 sxtw x3, w3[all …]
53 sxtw x6, w661 sxtw x6, w663 sxtw x7, w768 sxtw x6, w696 sxtw x6, w699 sxtw x6, w6135 sxtw x5, w5137 sxtw x6, w6
4 sxtw z0.d, p0/m, z0.s label10 sxtw z29.d, p7, z29.d label19 sxtw z0.b, p0/m, z0.b label24 sxtw z0.h, p0/m, z0.h label29 sxtw z0.s, p0/m, z0.s label38 sxtw z0.d, p8/m, z0.d label
10 sxtw z0.d, p0/m, z0.d label16 sxtw z31.d, p7/m, z31.d label32 sxtw z4.d, p7/m, z31.d label44 sxtw z4.d, p7/m, z31.d label
26 adr z0.s, [z0.s, z0.s, sxtw]41 adr z0.d, [z0.d, z0.s, sxtw]56 adr z0.d, [z0.d, z0.d, sxtw #4]66 adr z0.d, [z0.d, z0.d, sxtw #3]72 adr z0.d, [z0.d, z0.d, sxtw #3]
100 adr z0.d, [z0.d, z0.d, sxtw]106 adr z0.d, [z0.d, z0.d, sxtw #0]112 adr z0.d, [z0.d, z0.d, sxtw #1]118 adr z0.d, [z0.d, z0.d, sxtw #2]124 adr z0.d, [z0.d, z0.d, sxtw #3]
52 ldff1sh { z0.s }, p0/z, [x0, z0.s, sxtw]64 ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]88 ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]100 ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
52 ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]64 ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]88 ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]100 ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]
76 st1w { z0.s }, p0, [x0, z0.s, sxtw]88 st1w { z0.d }, p0, [x0, z0.d, sxtw]100 st1w { z0.s }, p0, [x0, z0.s, sxtw #2]112 st1w { z0.d }, p0, [x0, z0.d, sxtw #2]
70 ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]82 ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]106 ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]118 ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
8 ; CHECK-DAG: st1b { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw]9 ; CHECK-DAG: st1b { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw]10 ; CHECK-DAG: st1b { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw]11 ; CHECK-DAG: st1b { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw]20 ; CHECK-DAG: st1h { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #1]21 ; CHECK-DAG: st1h { {{z[0-9]+}}.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #1]42 ; CHECK-DAG: st1w { z0.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2]43 ; CHECK-DAG: st1w { z1.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2]44 ; CHECK-DAG: st1w { z2.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2]45 ; CHECK-DAG: st1w { z3.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2][all …]
8 ; LD1B, LD1W, LD1H, LD1D: base + 32-bit unscaled offset, sign (sxtw) or zero27 ; CHECK: ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]29 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i8(<vscale x 4 x i1> %pg,49 ; CHECK: ld1b { z0.d }, p0/z, [x0, z0.d, sxtw]51 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i8(<vscale x 2 x i1> %pg,72 ; CHECK: ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]74 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv4i16(<vscale x 4 x i1> %pg,94 ; CHECK: ld1h { z0.d }, p0/z, [x0, z0.d, sxtw]96 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.nxv2i16(<vscale x 2 x i1> %pg,116 ; CHECK: ld1w { z0.s }, p0/z, [x0, z0.s, sxtw][all …]
8 ; LDFF1B, LDFF1W, LDFF1H, LDFF1D: base + 32-bit unscaled offset, sign (sxtw) or zero27 ; CHECK: ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw]29 %load = call <vscale x 4 x i8> @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i8(<vscale x 4 x i1> %pg,49 ; CHECK: ldff1b { z0.d }, p0/z, [x0, z0.d, sxtw]51 %load = call <vscale x 2 x i8> @llvm.aarch64.sve.ldff1.gather.sxtw.nxv2i8(<vscale x 2 x i1> %pg,72 ; CHECK: ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]74 %load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.sxtw.nxv4i16(<vscale x 4 x i1> %pg,94 ; CHECK: ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw]96 %load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.sxtw.nxv2i16(<vscale x 2 x i1> %pg,116 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw][all …]
8 ; ST1B, ST1W, ST1H, ST1D: base + 32-bit unscaled offset, sign (sxtw) or zero28 ; CHECK: st1b { z0.s }, p0, [x0, z1.s, sxtw]31 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4i8(<vscale x 4 x i8> %data_trunc,52 ; CHECK: st1b { z0.d }, p0, [x0, z1.d, sxtw]55 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv2i8(<vscale x 2 x i8> %data_trunc,77 ; CHECK: st1h { z0.s }, p0, [x0, z1.s, sxtw]80 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv4i16(<vscale x 4 x i16> %data_trunc,101 ; CHECK: st1h { z0.d }, p0, [x0, z1.d, sxtw]104 call void @llvm.aarch64.sve.st1.scatter.sxtw.nxv2i16(<vscale x 2 x i16> %data_trunc,125 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, sxtw][all …]
8 ; ST1H, ST1W, ST1D: base + 32-bit scaled offset, sign (sxtw) or zero28 ; CHECK: st1h { z0.s }, p0, [x0, z1.s, sxtw #1]31 call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i16(<vscale x 4 x i16> %data_trunc,52 ; CHECK: st1h { z0.d }, p0, [x0, z1.d, sxtw #1]55 call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i16(<vscale x 2 x i16> %data_trunc,76 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, sxtw #2]78 call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv4i32(<vscale x 4 x i32> %data,99 ; CHECK: st1w { z0.d }, p0, [x0, z1.d, sxtw #2]102 call void @llvm.aarch64.sve.st1.scatter.sxtw.index.nxv2i32(<vscale x 2 x i32> %data_trunc,122 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, sxtw #2][all …]
8 ; LDFF1H, LDFF1W, LDFF1D: base + 32-bit scaled offset, sign (sxtw) or zero (uxtw)27 ; CHECK: ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw #1]29 …%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i16(<vscale x 4 x i1…49 ; CHECK: ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]51 …%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv2i16(<vscale x 2 x i1…71 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw #2]73 …%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv4i32(<vscale x 4 x i1…92 ; CHECK: ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]94 …%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ldff1.gather.sxtw.index.nxv2i32(<vscale x 2 x i1…113 ; CHECK: ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw #2][all …]
8 ; LD1H, LD1W, LD1D: base + 32-bit scaled offset, sign (sxtw) or zero (uxtw)27 ; CHECK: ld1h { z0.s }, p0/z, [x0, z0.s, sxtw #1]29 …%load = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i16(<vscale x 4 x i1> …49 ; CHECK: ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]51 …%load = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv2i16(<vscale x 2 x i1> …71 ; CHECK: ld1w { z0.s }, p0/z, [x0, z0.s, sxtw #2]73 …%load = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv4i32(<vscale x 4 x i1> …92 ; CHECK: ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]94 …%load = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.gather.sxtw.index.nxv2i32(<vscale x 2 x i1> …113 ; CHECK: ld1w { z0.s }, p0/z, [x0, z0.s, sxtw #2][all …]
18 ; CHECK-NEXT: prfb pldl1strm, p0, [x0, z0.s, sxtw]20 …call void @llvm.aarch64.sve.prfb.gather.sxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vsca…36 ; CHECK-NEXT: prfb pldl1strm, p0, [x0, z0.d, sxtw]38 …call void @llvm.aarch64.sve.prfb.gather.sxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vsca…63 ; CHECK-NEXT: prfh pldl1strm, p0, [x0, z0.s, sxtw #1]65 …call void @llvm.aarch64.sve.prfh.gather.sxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vsca…80 ; CHECK-NEXT: prfh pldl1strm, p0, [x0, z0.d, sxtw #1]82 …call void @llvm.aarch64.sve.prfh.gather.sxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, i8* %base, <vsca…108 ; CHECK-NEXT: prfw pldl1strm, p0, [x0, z0.s, sxtw #2]110 …call void @llvm.aarch64.sve.prfw.gather.sxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, i8* %base, <vsca…[all …]
44 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]55 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]113 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]124 ; CHECK: ldr {{x[0-9]+}}, [x1, w0, sxtw #3]252 ; CHECK-NOT: sxtw363 ; CHECK-NOT: sxtw374 ; CHECK: ldrb w0, [x0, w1, sxtw]386 ; CHECK: ldrh w0, [x0, w1, sxtw]398 ; CHECK: ldrb w0, [x0, w1, sxtw]410 ; CHECK: ldrh w0, [x0, w1, sxtw][all …]
19 ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw]47 ; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #1]71 ; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw]100 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2]124 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]152 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3]174 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]200 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2]224 ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]253 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3][all …]
96 sxtw x5,w5103 sxtw x5,w5144 sxtw x5,w5146 sxtw x7,w7158 sxtw x4,w4
85 sxtw x2, w286 sxtw x3, w387 sxtw x4, w488 sxtw x5, w5243 sxtw x2, w2244 sxtw x3, w3
24 str h0, [sp, w0, sxtw #1]27 str s0, [sp, w0, sxtw]87 # M3-NEXT: 2 3 1.00 * str h0, [sp, w0, sxtw #1]89 # M3-NEXT: 2 3 1.00 * str s0, [sp, w0, sxtw]110 # M4-NEXT: 2 3 0.50 * str h0, [sp, w0, sxtw #1]112 # M4-NEXT: 2 3 0.50 * str s0, [sp, w0, sxtw]133 # M5-NEXT: 1 1 0.50 * str h0, [sp, w0, sxtw #1]135 # M5-NEXT: 1 1 0.50 * str s0, [sp, w0, sxtw]