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Searched refs:u5 (Results 1 – 25 of 94) sorted by relevance

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/external/skia/tests/sksl/shared/
DHexUnsigned.asm.frag16 OpName %u5 "u5"
26 OpDecorate %u5 RelaxedPrecision
73 %u5 = OpVariable %_ptr_Function_uint Function
90 OpStore %u5 %uint_65534
91 %47 = OpLoad %uint %u5
93 OpStore %u5 %48
DHexUnsigned.glsl13 uint u5 = 65534u;
14 u5++;
DHexUnsigned.metal24 ushort u5 = 65534u;
25 u5++;
/external/e2fsprogs/lib/uuid/
Duuid.h58 #define UUID_DEFINE(name,u0,u1,u2,u3,u4,u5,u6,u7,u8,u9,u10,u11,u12,u13,u14,u15) \ argument
59 …static const uuid_t name __attribute__ ((unused)) = {u0,u1,u2,u3,u4,u5,u6,u7,u8,u9,u10,u11,u12,u13…
61 #define UUID_DEFINE(name,u0,u1,u2,u3,u4,u5,u6,u7,u8,u9,u10,u11,u12,u13,u14,u15) \ argument
62 static const uuid_t name = {u0,u1,u2,u3,u4,u5,u6,u7,u8,u9,u10,u11,u12,u13,u14,u15}
Duuid.h.in58 #define UUID_DEFINE(name,u0,u1,u2,u3,u4,u5,u6,u7,u8,u9,u10,u11,u12,u13,u14,u15) \ argument
59 …static const uuid_t name __attribute__ ((unused)) = {u0,u1,u2,u3,u4,u5,u6,u7,u8,u9,u10,u11,u12,u13…
61 #define UUID_DEFINE(name,u0,u1,u2,u3,u4,u5,u6,u7,u8,u9,u10,u11,u12,u13,u14,u15) \ argument
62 static const uuid_t name = {u0,u1,u2,u3,u4,u5,u6,u7,u8,u9,u10,u11,u12,u13,u14,u15}
/external/deqp-deps/glslang/Test/
Dhlsl.automap.frag18 RWByteAddressBuffer u5 : register(u5);
48 u5.Load(0);
Dhlsl.shift.per-set.frag20 RWByteAddressBuffer u5 : register(u4, space2);
50 u5.Load(0);
/external/skia/resources/sksl/shared/
DHexUnsigned.sksl12 ushort u5 = 0xfffe;
13 u5++;
/external/mesa3d/src/mesa/main/
Dformats.csv192 MESA_FORMAT_B5G6R5_UINT , packed, 1, 1, 1, u5 , u6 , u5 , , zyx1, rgb
193 MESA_FORMAT_R5G6B5_UINT , packed, 1, 1, 1, u5 , u6 , u5 , , xyz1, rgb
200 MESA_FORMAT_A1B5G5R5_UINT , packed, 1, 1, 1, u1 , u5 , u5 , u5 , wzyx, rgb
201 MESA_FORMAT_B5G5R5A1_UINT , packed, 1, 1, 1, u5 , u5 , u5 , u1 , zyxw, rgb
202 MESA_FORMAT_A1R5G5B5_UINT , packed, 1, 1, 1, u1 , u5 , u5 , u5 , yzwx, rgb
203 MESA_FORMAT_R5G5B5A1_UINT , packed, 1, 1, 1, u5 , u5 , u5 , u1 , xyzw, rgb
/external/libaom/libaom/aom_dsp/x86/
Dhighbd_subtract_sse2.c59 __m128i u0, u1, u2, u3, u4, u5, u6, u7; in subtract_4x8() local
69 u5 = _mm_loadl_epi64((__m128i const *)(src + 5 * src_stride)); in subtract_4x8()
87 x5 = _mm_sub_epi16(u5, v5); in subtract_4x8()
139 __m128i u0, u1, u2, u3, u4, u5, u6, u7; in subtract_8x8() local
148 u5 = _mm_loadu_si128((__m128i const *)(src + 5 * src_stride)); in subtract_8x8()
166 x5 = _mm_sub_epi16(u5, v5); in subtract_8x8()
Dfwd_txfm_impl_sse2.h321 const __m128i u5 = _mm_madd_epi16(t3, k__cospi_p24_p08); in FDCT8x8_2D() local
330 const __m128i v5 = _mm_add_epi32(u5, k__DCT_CONST_ROUNDING); in FDCT8x8_2D()
407 const __m128i u5 = _mm_madd_epi16(t3, k__cospi_p12_p20); in FDCT8x8_2D() local
416 const __m128i v5 = _mm_add_epi32(u5, k__DCT_CONST_ROUNDING); in FDCT8x8_2D()
/external/deqp-deps/glslang/Test/baseResults/
Dhlsl.automap.frag.out15 u5.@data: offset 0, type 1405, size 0, index 2, binding -1, stages 16, arrayStride 4, topLevelArray…
23 u5: offset -1, type ffffffff, size 4, index 2, binding 45, stages 16, numMembers 1
Dhlsl.shift.per-set.frag.out40 0:50 'u5' (layout( set=2 binding=4 row_major std430) buffer block{layout( row_major std430…
92 0:? 'u5' (layout( set=2 binding=4 row_major std430) buffer block{layout( row_major std430) buff…
142 0:50 'u5' (layout( set=2 binding=4 row_major std430) buffer block{layout( row_major std430…
194 0:? 'u5' (layout( set=2 binding=4 row_major std430) buffer block{layout( row_major std430) buff…
215 u5.@data: offset 0, type 1405, size 0, index 2, binding -1, stages 16, arrayStride 4, topLevelArray…
224 u5: offset -1, type ffffffff, size 4, index 2, binding 44, stages 16, numMembers 1
/external/libvpx/libvpx/vp9/encoder/x86/
Dvp9_dct_intrin_sse2.c283 __m128i u0, u1, u2, u3, u4, u5, u6, u7; in fdct8_sse2() local
312 u5 = _mm_madd_epi16(v3, k__cospi_p24_p08); in fdct8_sse2()
322 v5 = _mm_add_epi32(u5, k__DCT_CONST_ROUNDING); in fdct8_sse2()
331 u5 = _mm_srai_epi32(v5, DCT_CONST_BITS); in fdct8_sse2()
336 in[2] = _mm_packs_epi32(u4, u5); in fdct8_sse2()
390 u5 = _mm_add_epi32(v5, k__DCT_CONST_ROUNDING); in fdct8_sse2()
399 v5 = _mm_srai_epi32(u5, DCT_CONST_BITS); in fdct8_sse2()
430 __m128i u0, u1, u2, u3, u4, u5, u6, u7, u8, u9, u10, u11, u12, u13, u14, u15; in fadst8_sse2() local
463 u5 = _mm_madd_epi16(s3, k__cospi_p10_p22); in fadst8_sse2()
481 w5 = _mm_add_epi32(u5, u13); in fadst8_sse2()
[all …]
/external/llvm-project/libclc/generic/lib/math/
Dsincos_helpers.cl388 uint u0, u1, u2, u3, u4, u5, u6;
410 u5 = c.s1 ? q1.s2 : q1.s1;
411 u5 = c.s2 ? q1.s3 : u5;
412 u5 = c.s3 ? q2.s0 : u5;
422 uint v4 = bytealign(u5, u4, j);
423 uint v5 = bytealign(u6, u5, j);
/external/fdlibm/
De_lgamma_r.c129 u5 = 1.33810918536787660377e-02, /* 0x3F8B678B, 0xBF2BAB09 */ variable
271 p1 = y*(u0+y*(u1+y*(u2+y*(u3+y*(u4+y*u5)))));
/external/clang/test/SemaCXX/
Ddcl_init_aggr.cpp179 u u5 = { "asdf" }; // expected-error{{cannot initialize a member subobject of type 'int' with an lv… variable
/external/llvm-project/clang/test/SemaCXX/
Ddcl_init_aggr.cpp179 u u5 = { "asdf" }; // expected-error{{cannot initialize a member subobject of type 'int' with an lv… variable
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td48 def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$Rs, timm:$u5),
49 (S2_asl_i_r IntRegs:$Rs, imm:$u5)>;
50 def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$Rs, timm:$u5),
51 (S2_lsr_i_r IntRegs:$Rs, imm:$u5)>;
52 def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$Rs, timm:$u5),
53 (S2_asr_i_r IntRegs:$Rs, imm:$u5)>;
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dmem-ops-sub_01.ll2 ; Test that we do generate max #u5 in memops.
Dmem-ops-sub_i16_01.ll2 ; Test that we do not exceed #u5 in memops.
Dmem-ops-sub_i16.ll2 ; Test that we do generate max #u5 in memops.
Dmem-ops-sub.ll2 ; Test that we do not exceed #u5 in memops.
Dmapped_intrinsics.ll6 ; if (#u5 == 0) Assembler mapped to: Rd = Rs
7 ; else Rd = asr(Rs,#u5-1):rnd
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td48 def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$Rs, timm:$u5),
49 (S2_asl_i_r IntRegs:$Rs, imm:$u5)>;
50 def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$Rs, timm:$u5),
51 (S2_lsr_i_r IntRegs:$Rs, imm:$u5)>;
52 def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$Rs, timm:$u5),
53 (S2_asr_i_r IntRegs:$Rs, imm:$u5)>;

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