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Searched refs:u_bit_consecutive (Results 1 – 25 of 42) sorted by relevance

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/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_util.c328 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_inst_usage_mask()
330 read_mask = u_bit_consecutive(0, dim_layer_shadow) & 0xf; in tgsi_util_get_inst_usage_mask()
344 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_inst_usage_mask()
354 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_inst_usage_mask()
365 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_inst_usage_mask()
372 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_inst_usage_mask()
393 read_mask = u_bit_consecutive(0, dim); in tgsi_util_get_inst_usage_mask()
/external/mesa3d/src/gallium/drivers/lima/ir/pp/
Dnir.c45 dest->write_mask = u_bit_consecutive(0, ssa->num_components); in ppir_node_create_ssa()
113 u_bit_consecutive(0, 4)); in ppir_node_add_src()
248 &instr->src[0], u_bit_consecutive(0, instr->num_components)); in ppir_emit_discard_if()
273 mask = u_bit_consecutive(0, instr->num_components); in ppir_emit_intrinsic()
294 mask = u_bit_consecutive(0, instr->num_components); in ppir_emit_intrinsic()
322 mask = u_bit_consecutive(0, instr->num_components); in ppir_emit_intrinsic()
369 dest->write_mask = u_bit_consecutive(0, instr->num_components); in ppir_emit_intrinsic()
377 u_bit_consecutive(0, instr->num_components)); in ppir_emit_intrinsic()
464 mask = u_bit_consecutive(0, nir_tex_instr_dest_size(instr)); in ppir_emit_tex()
493 u_bit_consecutive(0, instr->coord_components)); in ppir_emit_tex()
Dregalloc.c279 ld_dest->write_mask = u_bit_consecutive(0, num_components); in ppir_update_spilled_src()
314 alu_dest->write_mask = u_bit_consecutive(0, num_components); in ppir_update_spilled_src()
362 load->dest.write_mask = u_bit_consecutive(0, num_components); in ppir_update_spilled_dest_load()
385 move_alu->dest.write_mask = u_bit_consecutive(0, num_components); in ppir_update_spilled_dest_load()
/external/mesa3d/src/gallium/auxiliary/nir/
Dnir_to_tgsi_info.c195 u_bit_consecutive(tex->sampler_index, 1); in scan_instruction()
797 info->const_buffers_declared = u_bit_consecutive(1, nir->info.num_ubos); in nir_tgsi_scan_shader()
812 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance); in nir_tgsi_scan_shader()
813 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance); in nir_tgsi_scan_shader()
/external/mesa3d/src/util/
Dbitscan.h272 u_bit_consecutive(unsigned start, unsigned count) in u_bit_consecutive() function
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pm4.c143 sctx->dirty_states |= u_bit_consecutive(0, SI_NUM_STATES); in si_pm4_reset_emitted()
Dsi_shaderlib_tgsi.c183 ureg_writemask(ureg_dst(values[i]), u_bit_consecutive(0, inst_dwords[i])); in si_create_dma_compute_shader()
195 struct ureg_dst dst = ureg_writemask(dstbuf, u_bit_consecutive(0, inst_dwords[d])); in si_create_dma_compute_shader()
Dsi_descriptors.c1866 u_bit_consecutive(SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS, SI_NUM_SHADER_DESCS); in si_mark_shader_pointers_dirty()
1879 sctx->shader_pointers_dirty = u_bit_consecutive(0, SI_NUM_DESCS); in si_shader_pointers_mark_dirty()
2054 sctx->shader_pointers_dirty &= ~u_bit_consecutive(SI_DESCS_RW_BUFFERS, SI_DESCS_FIRST_COMPUTE); in si_emit_graphics_shader_pointers()
2609 sctx->descriptors_dirty = u_bit_consecutive(0, SI_NUM_DESCS); in si_init_all_descriptors()
2674 const unsigned mask = u_bit_consecutive(0, SI_DESCS_FIRST_COMPUTE); in si_upload_graphics_shader_descriptors()
2684 u_bit_consecutive(SI_DESCS_FIRST_COMPUTE, SI_NUM_DESCS - SI_DESCS_FIRST_COMPUTE); in si_upload_compute_shader_descriptors()
2732 … u_bit_consecutive(0, current_shader[i]->cso->info.base.num_images)); in si_gfx_resources_check_encrypted()
2811 …si_image_views_check_encrypted(sctx, &sctx->images[sh], u_bit_consecutive(0, info->base.num_images… in si_compute_resources_check_encrypted()
Dsi_blit.c278 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1); in si_decompress_depth()
420 unsigned level_mask = u_bit_consecutive(first_level, last_level - first_level + 1); in si_blit_decompress_color()
752 if (shader_mask & u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)) { in si_decompress_textures()
1194 stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1, last_level - base_level); in si_generate_mipmap()
Dsi_gfx_cs.c490 u_bit_consecutive(0, ctx->framebuffer.state.nr_cbufs); in si_begin_new_gfx_cs()
494 ctx->framebuffer.dirty_cbufs = u_bit_consecutive(0, 8); in si_begin_new_gfx_cs()
Dsi_clear.c152 int max = u_bit_consecutive(0, desc->channel[i].size - 1); in vi_get_fast_clear_parameters()
160 unsigned max = u_bit_consecutive(0, desc->channel[i].size); in vi_get_fast_clear_parameters()
Dsi_debug.c792 enabled_constbuf = u_bit_consecutive(0, info->base.num_ubos); in si_dump_descriptors()
793 enabled_shaderbuf = u_bit_consecutive(0, info->base.num_ssbos); in si_dump_descriptors()
795 enabled_images = u_bit_consecutive(0, info->base.num_images); in si_dump_descriptors()
Dsi_state.h407 u_bit_consecutive(SI_DESCS_FIRST_SHADER + PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \
Dsi_state_draw.c220 assert((ring_va & u_bit_consecutive(0, 19)) == 0); in si_emit_derived_tess_state()
1807 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS)); in si_multi_draw_vbo()
/external/mesa3d/src/compiler/nir/
Dnir_lower_clip_disable.c124 if (clip_plane_enable == u_bit_consecutive(0, shader->info.clip_distance_array_size)) in nir_lower_clip_disable()
/external/mesa3d/src/mesa/state_tracker/
Dst_atom.c136 if (ctx->Scissor.EnableFlags & u_bit_consecutive(0, num_viewports)) in check_program_state()
Dst_atom_blend.c133 GLbitfield cb_mask = u_bit_consecutive(0, num_cb); in blend_per_rt()
/external/mesa3d/src/gallium/auxiliary/util/
Du_helpers.c55 *enabled_buffers &= ~u_bit_consecutive(start_slot, count); in util_set_vertex_buffers_mask()
Du_vbuf.c328 mgr->allowed_vb_mask = u_bit_consecutive(0, mgr->caps.max_vertex_buffers); in u_vbuf_create()
842 ve->incompatible_elem_mask = u_bit_consecutive(0, count); in u_vbuf_create_vertex_elements()
/external/mesa3d/src/gallium/drivers/virgl/
Dvirgl_context.c995 binding->view_enabled_mask &= ~u_bit_consecutive(start_slot, num_views); in virgl_set_sampler_views()
1178 vctx->atomic_buffer_enabled_mask &= ~u_bit_consecutive(start_slot, count); in virgl_set_hw_atomic_buffers()
1208 binding->ssbo_enabled_mask &= ~u_bit_consecutive(start_slot, count); in virgl_set_shader_buffers()
1263 binding->image_enabled_mask &= ~u_bit_consecutive(start_slot, count); in virgl_set_shader_images()
/external/mesa3d/src/amd/compiler/
Daco_insert_NOPs.cpp210 writemask |= u_bit_consecutive(start, end - start); in handle_raw_hazard_internal()
245 …l<Valu, Vintrp, Salu>(program, cur_block, min_states, op.physReg(), u_bit_consecutive(0, op.size()… in handle_raw_hazard()
/external/mesa3d/src/amd/common/
Dac_surface.c765 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx6_surface_settings()
1171 assert(xout.tileSwizzle <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx6_compute_surface()
1491 assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx9_compute_miptree()
1730 assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8)); in gfx9_compute_miptree()
/external/mesa3d/src/gallium/drivers/freedreno/
Dfreedreno_state.c131 const unsigned modified_bits = u_bit_consecutive(start, count); in fd_set_shader_buffers()
/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_winsys.c447 ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.num_render_backends); in do_winsys_init()
/external/mesa3d/src/amd/vulkan/
Dradv_meta_clear.c1635 int max = u_bit_consecutive(0, desc->channel[i].size - 1); in vi_get_fast_clear_parameters()
1643 unsigned max = u_bit_consecutive(0, desc->channel[i].size); in vi_get_fast_clear_parameters()

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