| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-mul.ll | 137 ; CHECK: umsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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| D | dp-3source.ll | 71 ; CHECK: umsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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| D | aarch64-fix-cortex-a53-835769.ll | 260 ; CHECK-NEXT: umsubl
263 ; CHECK-NOWORKAROUND-NEXT: umsubl
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-mul.ll | 137 ; CHECK: umsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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| D | dp-3source.ll | 71 ; CHECK: umsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}}
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| D | aarch64-fix-cortex-a53-835769.ll | 260 ; CHECK-NEXT: umsubl
263 ; CHECK-NOWORKAROUND-NEXT: umsubl
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| D | mul_pow2.ll | 221 ; CHECK-NEXT: umsubl x0, w0, w8, x1
227 ; GISEL-NEXT: umsubl x0, w0, w8, x1
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 467 umsubl x1, w2, w3, x4
476 ; CHECK: umsubl x1, w2, w3, x4 ; encoding: [0x41,0x90,0xa3,0x9b]
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| D | basic-a64-instructions.s | 1640 umsubl x3, w5, w2, x9
1641 umsubl xzr, w10, w11, x12
1642 umsubl x13, wzr, w14, x15
1643 umsubl x16, w17, wzr, x18
1644 umsubl x19, w20, w21, xzr
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| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | arm64-arithmetic-encoding.s | 467 umsubl x1, w2, w3, x4
476 ; CHECK: umsubl x1, w2, w3, x4 ; encoding: [0x41,0x90,0xa3,0x9b]
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| D | basic-a64-instructions.s | 1623 umsubl x3, w5, w2, x9
1624 umsubl xzr, w10, w11, x12
1625 umsubl x13, wzr, w14, x15
1626 umsubl x16, w17, wzr, x18
1627 umsubl x19, w20, w21, xzr
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| /external/capstone/suite/MC/AArch64/ |
| D | basic-a64-instructions.s.cs | 633 0xa3,0xa4,0xa2,0x9b = umsubl x3, w5, w2, x9
634 0x5f,0xb1,0xab,0x9b = umsubl xzr, w10, w11, x12
635 0xed,0xbf,0xae,0x9b = umsubl x13, wzr, w14, x15
636 0x30,0xca,0xbf,0x9b = umsubl x16, w17, wzr, x18
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-arithmetic.txt | 434 # CHECK: umsubl x1, w2, w3, x4
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| D | basic-a64-instructions.txt | 1199 # CHECK: umsubl x3, w5, w2, x9
1200 # CHECK: umsubl xzr, w10, w11, x12
1201 # CHECK: umsubl x13, wzr, w14, x15
1202 # CHECK: umsubl x16, w17, wzr, x18
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| /external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-arithmetic.txt | 434 # CHECK: umsubl x1, w2, w3, x4
|
| D | basic-a64-instructions.txt | 1186 # CHECK: umsubl x3, w5, w2, x9
1187 # CHECK: umsubl xzr, w10, w11, x12
1188 # CHECK: umsubl x13, wzr, w14, x15
1189 # CHECK: umsubl x16, w17, wzr, x18
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| /external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/ |
| D | A55-basic-instructions.s | 529 umsubl x3, w5, w2, x9 label
530 umsubl x16, w17, wzr, x18 label
1846 # CHECK-NEXT: 1 4 1.00 umsubl x3, w5, w2, x9
1847 # CHECK-NEXT: 1 4 1.00 umsubl x16, w17, wzr, x18
3029 … - - - - - - - - - 1.00 - umsubl x3, w5, w2, x9
3030 … - - - - - - - - 1.00 - umsubl x16, w17, wzr, x18
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| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 470 COMPARE(umsubl(x0, w1, w2, x3), "umsubl x0, w1, w2, x3"); in TEST()
471 COMPARE(umsubl(x30, w21, w22, x16), "umsubl x30, w21, w22, x16"); in TEST()
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| D | test-cpu-features-aarch64.cc | 523 TEST_NONE(umsubl_0, umsubl(x0, w1, w2, x3))
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 1011 void umsubl(const Register& xd,
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| D | assembler-aarch64.cc | 948 void Assembler::umsubl(const Register& xd, in umsubl() function in vixl::aarch64::Assembler
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| D | macro-assembler-aarch64.h | 2651 umsubl(rd, rn, rm, ra); in Umsubl()
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 3145 void umsubl(const Register& xd,
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| /external/capstone/arch/AArch64/ |
| D | AArch64MappingInsnOp.inc | 8449 { /* AArch64_UMSUBLrrr, ARM64_INS_UMSUBL: umsubl $rd, $rn, $rm, $ra */
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 740 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
|