Home
last modified time | relevance | path

Searched refs:uqdecp (Results 1 – 13 of 13) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Duqdecp.s10 uqdecp x0, p0.b label
16 uqdecp x0, p0.h label
22 uqdecp x0, p0.s label
28 uqdecp x0, p0.d label
34 uqdecp wzr, p15.b label
40 uqdecp wzr, p15.h label
46 uqdecp wzr, p15.s label
52 uqdecp wzr, p15.d label
58 uqdecp z0.h, p0 label
64 uqdecp z0.h, p0.h label
[all …]
Dsqincp-diagnostics.s6 uqdecp sp, p0 label
11 uqdecp z0.b, p0 label
16 uqdecp x0, p0.b, w0 label
21 uqdecp x0, p0.b, x1 label
30 uqdecp x0, p0 label
35 uqdecp x0, p0/z label
40 uqdecp x0, p0/m label
45 uqdecp x0, p0.q label
Duqdecp-diagnostics.s3 uqdecp z0.d, p0.b label
8 uqdecp z0.d, p0.q label
18 uqdecp z0.d, p0 label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-uqdec.ll59 ; CHECK: uqdecp z0.h, p0
61 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdecp.nxv8i16(<vscale x 8 x i16> %a,
68 ; CHECK: uqdecp z0.s, p0
70 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecp.nxv4i32(<vscale x 4 x i32> %a,
77 ; CHECK: uqdecp z0.d, p0
79 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecp.nxv2i64(<vscale x 2 x i64> %a,
170 ; CHECK: uqdecp w0, p0.b
172 %out = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32 %a, <vscale x 16 x i1> %b)
178 ; CHECK: uqdecp w0, p0.h
180 %out = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32 %a, <vscale x 8 x i1> %b)
[all …]
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc1962 COMPARE_PREFIX(uqdecp(w3, p13.VnB()), "uqdecp w3, p13.b"); in TEST()
1963 COMPARE_PREFIX(uqdecp(w3, p13.VnH()), "uqdecp w3, p13.h"); in TEST()
1964 COMPARE_PREFIX(uqdecp(w3, p13.VnS()), "uqdecp w3, p13.s"); in TEST()
1965 COMPARE_PREFIX(uqdecp(w3, p13.VnD()), "uqdecp w3, p13.d"); in TEST()
1966 COMPARE_PREFIX(uqdecp(x19, p0.VnB()), "uqdecp x19, p0.b"); in TEST()
1967 COMPARE_PREFIX(uqdecp(x19, p0.VnH()), "uqdecp x19, p0.h"); in TEST()
1968 COMPARE_PREFIX(uqdecp(x19, p0.VnS()), "uqdecp x19, p0.s"); in TEST()
1969 COMPARE_PREFIX(uqdecp(x19, p0.VnD()), "uqdecp x19, p0.d"); in TEST()
1970 COMPARE_PREFIX(uqdecp(z15.VnH(), p9), "uqdecp z15.h, p9"); in TEST()
1971 COMPARE_PREFIX(uqdecp(z15.VnS(), p9), "uqdecp z15.s, p9"); in TEST()
[all …]
Dtest-api-movprfx-aarch64.cc1187 __ uqdecp(z31.VnS(), p5); in TEST() local
1588 __ uqdecp(z12.VnS(), p7); in TEST() local
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12607 "umullb\006umullt\005uqadd\006uqdecb\006uqdecd\006uqdech\006uqdecp\006uq"
19593 …{ 6544 /* uqdecp */, AArch64::UQDECP_WP_H, Convert__Reg1_0__SVEPredicateHReg1_1__Tie0_1_1, AMFBS_H…
19594 …{ 6544 /* uqdecp */, AArch64::UQDECP_WP_S, Convert__Reg1_0__SVEPredicateSReg1_1__Tie0_1_1, AMFBS_H…
19595 …{ 6544 /* uqdecp */, AArch64::UQDECP_WP_D, Convert__Reg1_0__SVEPredicateDReg1_1__Tie0_1_1, AMFBS_H…
19596 …{ 6544 /* uqdecp */, AArch64::UQDECP_WP_B, Convert__Reg1_0__SVEPredicateBReg1_1__Tie0_1_1, AMFBS_H…
19597 …{ 6544 /* uqdecp */, AArch64::UQDECP_XP_H, Convert__Reg1_0__SVEPredicateHReg1_1__Tie0_1_1, AMFBS_H…
19598 …{ 6544 /* uqdecp */, AArch64::UQDECP_XP_S, Convert__Reg1_0__SVEPredicateSReg1_1__Tie0_1_1, AMFBS_H…
19599 …{ 6544 /* uqdecp */, AArch64::UQDECP_XP_D, Convert__Reg1_0__SVEPredicateDReg1_1__Tie0_1_1, AMFBS_H…
19600 …{ 6544 /* uqdecp */, AArch64::UQDECP_XP_B, Convert__Reg1_0__SVEPredicateBReg1_1__Tie0_1_1, AMFBS_H…
19601 …{ 6544 /* uqdecp */, AArch64::UQDECP_ZP_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicateHReg1_…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td919 defm UQDECP_WP : sve_int_count_r_u32<0b01100, "uqdecp", int_aarch64_sve_uqdecp_n32>;
920 defm UQDECP_XP : sve_int_count_r_x64<0b01110, "uqdecp", int_aarch64_sve_uqdecp_n64>;
927 defm UQDECP_ZP : sve_int_count_v<0b01100, "uqdecp", int_aarch64_sve_uqdecp>;
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1365 defm UQDECP_WP : sve_int_count_r_u32<0b01100, "uqdecp", int_aarch64_sve_uqdecp_n32>;
1366 defm UQDECP_XP : sve_int_count_r_x64<0b01110, "uqdecp", int_aarch64_sve_uqdecp_n64>;
1373 defm UQDECP_ZP : sve_int_count_v<0b01100, "uqdecp", int_aarch64_sve_uqdecp>;
/external/vixl/src/aarch64/
Dmacro-assembler-aarch64.h6152 uqdecp(rd, pg); in Uqdecp()
6155 uqdecp(rd.W(), pg); in Uqdecp()
6166 uqdecp(zd, pg); in Uqdecp()
Dassembler-aarch64.h5697 void uqdecp(const Register& rdn, const PRegisterWithLaneSize& pg);
5700 void uqdecp(const ZRegister& zdn, const PRegister& pg);
Dassembler-sve-aarch64.cc2130 void Assembler::uqdecp(const Register& rdn, const PRegisterWithLaneSize& pg) { in uqdecp() function in vixl::aarch64::Assembler
2143 void Assembler::uqdecp(const ZRegister& zdn, const PRegister& pg) { in uqdecp() function in vixl::aarch64::Assembler
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc809 "llvm.aarch64.sve.uqdecp",
810 "llvm.aarch64.sve.uqdecp.n32",
811 "llvm.aarch64.sve.uqdecp.n64",
10942 1, // llvm.aarch64.sve.uqdecp
10943 1, // llvm.aarch64.sve.uqdecp.n32
10944 1, // llvm.aarch64.sve.uqdecp.n64