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Searched refs:urshr (Results 1 – 25 of 48) sorted by relevance

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/external/llvm-project/llvm/test/MC/AArch64/SVE2/
Durshr-diagnostics.s3 urshr z18.b, p0/m, z18.b, #0 label
8 urshr z1.b, p0/m, z1.b, #9 label
13 urshr z21.h, p0/m, z21.h, #0 label
18 urshr z14.h, p0/m, z14.h, #17 label
23 urshr z6.s, p0/m, z6.s, #0 label
28 urshr z23.s, p0/m, z23.s, #33 label
33 urshr z3.d, p0/m, z3.d, #0 label
38 urshr z25.d, p0/m, z25.d, #65 label
47 urshr z0.b, p0/m, z1.b, #1 label
56 urshr z0.b, p0/m, z0.d, #1 label
[all …]
Durshr.s10 urshr z0.b, p0/m, z0.b, #1 label
16 urshr z31.b, p0/m, z31.b, #8 label
22 urshr z0.h, p0/m, z0.h, #1 label
28 urshr z31.h, p0/m, z31.h, #16 label
34 urshr z0.s, p0/m, z0.s, #1 label
40 urshr z31.s, p0/m, z31.s, #32 label
46 urshr z0.d, p0/m, z0.d, #1 label
52 urshr z31.d, p0/m, z31.d, #64 label
68 urshr z31.d, p0/m, z31.d, #64 label
80 urshr z31.d, p0/m, z31.d, #64 label
/external/capstone/suite/MC/AArch64/
Dneon-simd-shift.s.cs37 0x20,0x24,0x0d,0x2f = urshr v0.8b, v1.8b, #3
38 0x20,0x24,0x1d,0x2f = urshr v0.4h, v1.4h, #3
39 0x20,0x24,0x3d,0x2f = urshr v0.2s, v1.2s, #3
40 0x20,0x24,0x0d,0x6f = urshr v0.16b, v1.16b, #3
41 0x20,0x24,0x1d,0x6f = urshr v0.8h, v1.8h, #3
42 0x20,0x24,0x3d,0x6f = urshr v0.4s, v1.4s, #3
43 0x20,0x24,0x7d,0x6f = urshr v0.2d, v1.2d, #3
Dneon-scalar-shift-imm.s.cs5 0xf4,0x26,0x61,0x7f = urshr d20, d23, #31
/external/llvm/test/MC/AArch64/
Dneon-simd-shift.s103 urshr v0.8b, v1.8b, #3
104 urshr v0.4h, v1.4h, #3
105 urshr v0.2s, v1.2s, #3
106 urshr v0.16b, v1.16b, #3
107 urshr v0.8h, v1.8h, #3
108 urshr v0.4s, v1.4s, #3
109 urshr v0.2d, v1.2d, #3
Dneon-scalar-shift-imm.s29 urshr d20, d23, #31
Darm64-advsimd.s1392 urshr d0, d0, #1 define
1441 ; CHECK: urshr d0, d0, #1 ; encoding: [0x00,0x24,0x7f,0x7f]
1588 urshr.8b v0, v0, #1
1589 urshr.16b v0, v0, #2
1590 urshr.4h v0, v0, #3
1591 urshr.8h v0, v0, #4
1592 urshr.2s v0, v0, #5
1593 urshr.4s v0, v0, #6
1594 urshr.2d v0, v0, #7
1760 ; CHECK: urshr.8b v0, v0, #1 ; encoding: [0x00,0x24,0x0f,0x2f]
[all …]
Dneon-diagnostics.s1543 urshr v0.8b, v1.8h, #3
1544 urshr v0.4h, v1.4s, #3
1545 urshr v0.2s, v1.2d, #3
1546 urshr v0.16b, v1.16b, #9
1547 urshr v0.8h, v1.8h, #17
1548 urshr v0.4s, v1.4s, #33
1549 urshr v0.2d, v1.2d, #65
4943 urshr d20, d23, #99
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-simd-shift.s103 urshr v0.8b, v1.8b, #3
104 urshr v0.4h, v1.4h, #3
105 urshr v0.2s, v1.2s, #3
106 urshr v0.16b, v1.16b, #3
107 urshr v0.8h, v1.8h, #3
108 urshr v0.4s, v1.4s, #3
109 urshr v0.2d, v1.2d, #3
Dneon-scalar-shift-imm.s29 urshr d20, d23, #31
Darm64-advsimd.s1392 urshr d0, d0, #1 define
1441 ; CHECK: urshr d0, d0, #1 ; encoding: [0x00,0x24,0x7f,0x7f]
1588 urshr.8b v0, v0, #1
1589 urshr.16b v0, v0, #2
1590 urshr.4h v0, v0, #3
1591 urshr.8h v0, v0, #4
1592 urshr.2s v0, v0, #5
1593 urshr.4s v0, v0, #6
1594 urshr.2d v0, v0, #7
1760 ; CHECK: urshr.8b v0, v0, #1 ; encoding: [0x00,0x24,0x0f,0x2f]
[all …]
Dneon-diagnostics.s1548 urshr v0.8b, v1.8h, #3
1549 urshr v0.4h, v1.4s, #3
1550 urshr v0.2s, v1.2d, #3
1551 urshr v0.16b, v1.16b, #9
1552 urshr v0.8h, v1.8h, #17
1553 urshr v0.4s, v1.4s, #33
1554 urshr v0.2d, v1.2d, #65
4883 urshr d20, d23, #99
/external/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/
Dscalar-shifts.c234 return urshr(value, 22); in test_urshr()
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dscalar-shifts.ll252 ; CHECK-NEXT: urshr r0, #22
255 %0 = call i32 @llvm.arm.mve.urshr(i32 %value, i32 22)
259 declare i32 @llvm.arm.mve.urshr(i32, i32)
/external/llvm-project/llvm/test/MC/ARM/
Dmve-scalar-shift.s158 # CHECK: urshr r0, #10 @ encoding: [0x50,0xea,0x9f,0x2f]
160 urshr r0, #10 label
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dmve-scalar-shift.txt86 # CHECK: urshr r0, #10 @ encoding: [0x50,0xea,0x9f,0x2f]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve2-intrinsics-uniform-dsp.ll1701 ; CHECK: urshr z0.b, p0/m, z0.b, #4
1703 %out = call <vscale x 16 x i8> @llvm.aarch64.sve.urshr.nxv16i8(<vscale x 16 x i1> %pg,
1711 ; CHECK: urshr z0.h, p0/m, z0.h, #13
1713 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.urshr.nxv8i16(<vscale x 8 x i1> %pg,
1721 ; CHECK: urshr z0.s, p0/m, z0.s, #1
1723 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.urshr.nxv4i32(<vscale x 4 x i1> %pg,
1731 ; CHECK: urshr z0.d, p0/m, z0.d, #24
1733 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.urshr.nxv2i64(<vscale x 2 x i1> %pg,
2078 declare <vscale x 16 x i8> @llvm.aarch64.sve.urshr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, …
2079 declare <vscale x 8 x i16> @llvm.aarch64.sve.urshr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i…
[all …]
Darm64-vshift.ll443 ;CHECK: urshr.8b
451 ;CHECK: urshr.4h
459 ;CHECK: urshr.2s
467 ;CHECK: urshr.16b
475 ;CHECK: urshr.8h
483 ;CHECK: urshr.4s
491 ;CHECK: urshr.2d
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt810 # CHECK: urshr v0.8b, v1.8b, #3
811 # CHECK: urshr v0.4h, v1.4h, #3
812 # CHECK: urshr v0.2s, v1.2s, #3
813 # CHECK: urshr v0.16b, v1.16b, #3
814 # CHECK: urshr v0.8h, v1.8h, #3
815 # CHECK: urshr v0.4s, v1.4s, #3
816 # CHECK: urshr v0.2d, v1.2d, #3
1834 # CHECK: urshr d20, d23, #31
Darm64-advsimd.txt1845 # CHECK: urshr d0, d0, #0x3f
2163 # CHECK: urshr.8b v0, v0, #0x7
2164 # CHECK: urshr.16b v0, v0, #0x6
2165 # CHECK: urshr.4h v0, v0, #0xd
2166 # CHECK: urshr.8h v0, v0, #0xc
2167 # CHECK: urshr.2s v0, v0, #0x1b
2168 # CHECK: urshr.4s v0, v0, #0x1a
2169 # CHECK: urshr.2d v0, v0, #0x39
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt810 # CHECK: urshr v0.8b, v1.8b, #3
811 # CHECK: urshr v0.4h, v1.4h, #3
812 # CHECK: urshr v0.2s, v1.2s, #3
813 # CHECK: urshr v0.16b, v1.16b, #3
814 # CHECK: urshr v0.8h, v1.8h, #3
815 # CHECK: urshr v0.4s, v1.4s, #3
816 # CHECK: urshr v0.2d, v1.2d, #3
1834 # CHECK: urshr d20, d23, #31
Darm64-advsimd.txt1845 # CHECK: urshr d0, d0, #0x3f
2163 # CHECK: urshr.8b v0, v0, #0x7
2164 # CHECK: urshr.16b v0, v0, #0x6
2165 # CHECK: urshr.4h v0, v0, #0xd
2166 # CHECK: urshr.8h v0, v0, #0xc
2167 # CHECK: urshr.2s v0, v0, #0x1b
2168 # CHECK: urshr.4s v0, v0, #0x1a
2169 # CHECK: urshr.2d v0, v0, #0x39
/external/llvm/test/CodeGen/AArch64/
Darm64-vshift.ll443 ;CHECK: urshr.8b
451 ;CHECK: urshr.4h
459 ;CHECK: urshr.2s
467 ;CHECK: urshr.16b
475 ;CHECK: urshr.8h
483 ;CHECK: urshr.4s
491 ;CHECK: urshr.2d
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2401 __ urshr(d4, d13, 49); in GenerateTestSequenceNEON() local
2402 __ urshr(v2.V16B(), v20.V16B(), 1); in GenerateTestSequenceNEON() local
2403 __ urshr(v13.V2D(), v11.V2D(), 51); in GenerateTestSequenceNEON() local
2404 __ urshr(v21.V2S(), v31.V2S(), 10); in GenerateTestSequenceNEON() local
2405 __ urshr(v21.V4H(), v17.V4H(), 11); in GenerateTestSequenceNEON() local
2406 __ urshr(v4.V4S(), v22.V4S(), 1); in GenerateTestSequenceNEON() local
2407 __ urshr(v0.V8B(), v1.V8B(), 7); in GenerateTestSequenceNEON() local
2408 __ urshr(v13.V8H(), v20.V8H(), 1); in GenerateTestSequenceNEON() local
/external/vixl/test/test-trace-reference/
Dlog-disasm2056 0x~~~~~~~~~~~~~~~~ 7f4f25a4 urshr d4, d13, #49
2057 0x~~~~~~~~~~~~~~~~ 6f0f2682 urshr v2.16b, v20.16b, #1
2058 0x~~~~~~~~~~~~~~~~ 6f4d256d urshr v13.2d, v11.2d, #51
2059 0x~~~~~~~~~~~~~~~~ 2f3627f5 urshr v21.2s, v31.2s, #10
2060 0x~~~~~~~~~~~~~~~~ 2f152635 urshr v21.4h, v17.4h, #11
2061 0x~~~~~~~~~~~~~~~~ 6f3f26c4 urshr v4.4s, v22.4s, #1
2062 0x~~~~~~~~~~~~~~~~ 2f092420 urshr v0.8b, v1.8b, #7
2063 0x~~~~~~~~~~~~~~~~ 6f1f268d urshr v13.8h, v20.8h, #1

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