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Searched refs:usdot (Results 1 – 10 of 10) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dmatrix-multiply-int8-diagnostics.s33 usdot z0.d, z1.b, z2.b label
35 usdot z0.s, z1.s, z2.b label
37 usdot z0.s, z1.b, z2.h label
43 usdot z0.s, z1.b, z2.b label
52 usdot z0.h, z1.b, z2.b[0] label
56 usdot z0.s, z1.b, z2.s[0] label
60 usdot z0.s, z1.b, z9.b[0] label
66 usdot z0.s, z1.b, z2.b[4] label
74 usdot z0.s, z1.b, z2.b[0] label
Dmatrix-multiply-int8.s72 usdot z0.s, z1.b, z2.b label
85 usdot z0.s, z1.b, z2.b label
95 usdot z0.s, z1.b, z2.b[0] label
114 usdot z0.s, z1.b, z2.b[0] label
/external/llvm-project/llvm/test/MC/AArch64/
Darmv8.6a-simd-matmul-error.s11 usdot v3.4s, v15.8b, v30.8b label
13 usdot v3.2s, v15.16b, v30.16b label
17 usdot v31.2s, v1.8b, v2.4b[4] label
19 usdot v31.4s, v1.16b, v2.4b[4] label
27 usdot v31.4s, v1.8b, v2.4b[0] label
29 usdot v31.2s, v1.16b, v2.4b[0] label
Darmv8.6a-simd-matmul.s18 usdot v3.2s, v15.8b, v30.8b label
19 usdot v3.4s, v15.16b, v30.16b label
27 usdot v31.2s, v1.8b, v2.4b[3] label
28 usdot v31.4s, v1.16b, v2.4b[3] label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-matmul.ll27 define <2 x i32> @usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) {
29 ; CHECK-LABEL: usdot.v2i32.v8i8
30 ; CHECK: usdot v0.2s, v1.8b, v2.8b
31 …%vusdot1.i = tail call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8…
38 ; CHECK: usdot v0.2s, v1.8b, v2.4b[0]
42 …%vusdot1.i = tail call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8…
53 …%vusdot1.i = tail call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %1, <8…
60 ; CHECK: usdot v0.2s, v1.8b, v2.4b[0]
64 …%vusdot1.i = tail call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8…
75 …%vusdot1.i = tail call <2 x i32> @llvm.aarch64.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %1, <8…
[all …]
Dsve-intrinsics-matmul-int8.ll34 define <vscale x 4 x i32> @usdot(<vscale x 4 x i32> %r, <vscale x 16 x i8> %a, <vscale x 16 x i8> %…
36 ; CHECK-LABEL: usdot:
37 ; CHECK-NEXT: usdot z0.s, z1.b, z2.b
39 …%val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.nxv4i32(<vscale x 4 x i32> %r, <vscale…
46 ; CHECK-NEXT: usdot z0.s, z1.b, z2.b[0]
48 …%val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %r, <v…
55 ; CHECK-NEXT: usdot z0.s, z1.b, z2.b[1]
57 …%val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %r, <v…
64 ; CHECK-NEXT: usdot z0.s, z1.b, z2.b[2]
66 …%val = tail call <vscale x 4 x i32> @llvm.aarch64.sve.usdot.lane.nxv4i32(<vscale x 4 x i32> %r, <v…
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Darm-matmul.ll27 define <2 x i32> @usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i8> %b) {
29 ; CHECK-LABEL: usdot.v2i32.v8i8
31 …%vusdot1.i = tail call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i…
42 …%vusdot1.i = tail call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %a, <8 x i…
53 …%vusdot1.i = tail call <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32> %r, <8 x i8> %1, <8 x i…
64 …%vusdot1.i = tail call <4 x i32> @llvm.arm.neon.usdot.v4i32.v16i8(<4 x i32> %r, <16 x i8> %a, <16 …
75 …%vusdot1.i = tail call <4 x i32> @llvm.arm.neon.usdot.v4i32.v16i8(<4 x i32> %r, <16 x i8> %1, <16 …
82 declare <2 x i32> @llvm.arm.neon.usdot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>) #2
83 declare <4 x i32> @llvm.arm.neon.usdot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>) #2
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Darmv8.6a-simd-matmul.txt17 # CHECK: usdot v3.2s, v15.8b, v30.8b
18 # CHECK: usdot v3.4s, v15.16b, v30.16b
24 # CHECK: usdot v31.2s, v1.8b, v2.4b[3]
25 # CHECK: usdot v31.4s, v1.16b, v2.4b[3]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td2354 defm USDOT_ZZZ : sve_int_dot_mixed<"usdot", int_aarch64_sve_usdot>;
2355 defm USDOT_ZZZI : sve_int_dot_mixed_indexed<0, "usdot", int_aarch64_sve_usdot_lane>;
DAArch64InstrInfo.td832 defm USDOT : SIMDThreeSameVectorDot<0, 1, "usdot", int_aarch64_neon_usdot>;
833 defm USDOTlane : SIMDThreeSameVectorDotIndex<0, 1, 0b10, "usdot", int_aarch64_neon_usdot>;
835 // sudot lane has a pattern where usdot is expected (there is no sudot).