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Searched refs:v128i1 (Results 1 – 18 of 18) sorted by relevance

/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td46 def : Pat <(v128i1 (bitconvert (v32i32 HvxVR:$src1))),
47 (v128i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
49 def : Pat <(v128i1 (bitconvert (v64i16 HvxVR:$src1))),
50 (v128i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
52 def : Pat <(v128i1 (bitconvert (v128i8 HvxVR:$src1))),
53 (v128i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
55 def : Pat <(v32i32 (bitconvert (v128i1 HvxQR:$src1))),
56 (v32i32 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
58 def : Pat <(v64i16 (bitconvert (v128i1 HvxQR:$src1))),
59 (v64i16 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
DHexagonRegisterInfo.td322 [v64i1, v128i1, v64i1]>;
338 [v64i1, v128i1, v64i1]>;
DHexagonISelDAGToDAGHVX.cpp2252 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v128i1); in SelectHVXDualOutput()
2266 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v128i1); in SelectHVXDualOutput()
DHexagonISelLoweringHVX.cpp56 addRegisterClass(MVT::v128i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
79 setOperationAction(ISD::BITCAST, MVT::v128i1, Custom); in initializeHVXLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h67 v128i1 = 21, // 128 x i1 enumerator
350 return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8 || in is128BitVector()
435 case v128i1: in getVectorElementType()
563 case v128i1: in getVectorNumElements()
758 case v128i1: in getSizeInBits()
930 if (NumElements == 128) return MVT::v128i1; in getVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h68 v128i1 = 22, // 128 x i1 enumerator
381 return (SimpleTy == MVT::v128i1 || SimpleTy == MVT::v16i8 || in is128BitVector()
502 case v128i1: in getVectorElementType()
658 case v128i1: in getVectorNumElements()
890 case v128i1: in getSizeInBits()
1117 if (NumElements == 128) return MVT::v128i1; in getVectorVT()
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dreduce-xor.ll164 …imated cost of 52 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
175 …imated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
186 …imated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
197 …imated cost of 49 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
208 …imated cost of 29 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
219 …mated cost of 140 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
230 …mated cost of 776 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
241 …mated cost of 140 for instruction: %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
251 %V128 = call i1 @llvm.vector.reduce.xor.v128i1(<128 x i1> undef)
289 declare i1 @llvm.vector.reduce.xor.v128i1(<128 x i1>)
Dreduce-or.ll164 …stimated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
175 …stimated cost of 7 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
186 …stimated cost of 5 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
197 …timated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
208 …timated cost of 14 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
219 …timated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
229 %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef)
267 declare i1 @llvm.vector.reduce.or.v128i1(<128 x i1>)
Dreduce-and.ll164 …timated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
175 …timated cost of 7 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
186 …timated cost of 5 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
197 …imated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
208 …imated cost of 14 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
219 …imated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
229 %V128 = call i1 @llvm.vector.reduce.and.v128i1(<128 x i1> undef)
267 declare i1 @llvm.vector.reduce.and.v128i1(<128 x i1>)
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dstore-vector-pred.ll3 ; This test checks that store a vector predicate of type v128i1 is lowered
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td42 def v128i1 : ValueType<128, 21>; // 128 x i1 vector value
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp166 case MVT::v128i1: return VectorType::get(Type::getInt1Ty(Context), 128); in getTypeForEVT()
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td44 def v128i1 : ValueType<128, 22>; // 128 x i1 vector value
/external/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp212 case MVT::v128i1: in getTypeForEVT()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp88 case MVT::v128i1: return "MVT::v128i1"; in getEnumName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td302 [v64i1, v128i1, v64i1]>;
DHexagonISelLoweringHVX.cpp52 addRegisterClass(MVT::v128i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsics.td264 def llvm_v128i1_ty : LLVMType<v128i1>; // 128 x i1